Datasheet

SPI SHIFT REGISTER
DAC8234
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........................................................................................................................................... SBAS464A AUGUST 2009 REVISED SEPTEMBER 2009
The SPI Shift Register is 24 bits wide, as shown in Table 2 . By default, the SPI shift register resets to 000000h at
power-on or after a reset.
Table 2. SPI Shift Register Format
MSB
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15:DB2 DB1:DB0
R/ W 0 0 0 A3 A2 A1 A0 DATA Rsvd
(1)
(1) Writing to a reserved bit has no effect; reading the bit returns ' 0 ' .
R/ W— Indicates a read from or a write to the addressed register.
R/ W = '0' sets a write operation and the data are written to the specified register.
R/ W = '1' sets a read-back operation. For read operation, bits A3 to A0 select the register to be read. The
remaining are don t care bits. During the next SPI operation, the data appearing on SDO pin are from the
previously addressed register.
[A3:A0] Address bits that specify which register is accessed.
DATA 14 data bits
All DAC8234 registers (command registers and data registers) are 16-bit. Table 3 shows the register map.
Table 3. Register Map
ADDRESS BITS DATA BITS
DB5: DB1:
A3 A2 A1 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6
DB2 DB0 REGISTER
GAIN Command
0 0 0 0 A/B LD RST PD-A PD-B Rsvd
(1)
GPIO-1 GPIO-0 DSDO NOP Rsvd
(1)
Bits Register
0 0 0 1 MDAC-3 MDAC-2 MDAC-1 MDAC-0 AIN Reserved
(1)
Monitor Register
0 1 0 0 D13:D0 Rsvd
(1)
DAC-0
0 1 0 1 D13:D0 Rsvd
(1)
DAC-1
0 1 1 0 D13:D0 Rsvd
(1)
DAC-2
0 1 1 1 D13:D0 Rsvd
(1)
DAC-3
1 0 0 0 Reserved
(1)
Z8:Z0 Zero Register-0
1 0 0 1 Reserved
(1)
Z8:Z0 Zero Register-1
1 0 1 0 Reserved
(1)
Z8:Z0 Zero Register-2
1 0 1 1 Reserved
(1)
Z8:Z0 Zero Register-3
1 1 0 0 Reserved
(1)
G7:G0 Gain Register-0
1 1 0 1 Reserved
(1)
G7:G0 Gain Register-1
1 1 1 0 Reserved
(1)
G7:G0 Gain Register-2
1 1 1 1 Reserved
(1)
G7:G0 Gain Register-3
Others Reserved
(1)
(1) Writing to a reserved bit has no effect; reading the bit returns ' 0 ' .
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