Datasheet

THEORY OF OPERATION
DAC ARCHITECTURE
V
OUT
SGND
2R2R
S17 S16 S12
2R 2R
S11
ThreeMSBsDecodedInto
SevenEqualSegments
2R
S10 S9
2R
R R R R
S8
2R
S0
2R 2R
R
FB
11-BitR-2RLadder
FromReference
BufferOutput
CHANNEL GROUPS
USER-CALIBRATION FOR ZERO ERROR AND GAIN ERROR
DAC8234
www.ti.com ........................................................................................................................................... SBAS464A – AUGUST 2009 – REVISED SEPTEMBER 2009
The DAC8234 is a highly-integrated, quad-channel, 14-bit, voltage-output DAC with internal reference buffers
and output buffers. Each channel consists of an R-2R ladder configuration with the three MSBs segmented,
followed by an operational amplifier, as shown in Figure 41 . The DAC8234 has a high-impedance, buffered
reference input; the output of the reference buffers drives the R-2R ladders. The output buffer is designed to
allow user-configurable adjustments, giving the DAC8234 four different output voltage range settings. With the
production trim process, this device has excellent dc accuracy and ac performance.
Figure 41. DAC8234 Architecture
The four DAC channels are arranged into two groups (A and B) with two channels per group. Group A consists
of DAC-0 and DAC-1, and Group B consists of DAC-2 and DAC-3. The two DAC channels of Group A derive
their reference voltage from REF-A, and those of Group B from REF-B.
The DAC8234 implements a user-calibration function that allows for trimming the system gain and zero errors.
Each DAC channel has a Gain Register and Zero Register and the DAC output is calibrated according to the
value of the corresponding registers. The range of gain adjustment is typically ± 0.195% of full-scale with 0.25
LSB per step. The zero code adjustment is typically ± 0.0488% of full-scale with 0.03125 LSB per step. The input
data format of the Gain and Zero registers is twos complement. Refer to Table 9 and Table 10 for more details.
If the system-level calibration is not needed, these registers should be left at the respective default values
(0000h) at power-on.
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