Datasheet

Case5:ReadbackforStand-alonemode.
t
8
t
4
t
1
t
2
t
7
t
3
t
6
t
5
BIT23 BIT22
InputWordSpecifiesRegistertobeRead WriteNOPCommand
DatafromtheSelectedRegister
BIT0
BIT23
BIT23
BIT22
BIT22
BIT1
BIT1
BIT0
BIT0
InputDataRegisterUpdated
CS
SCLK
SDI
SDO
LDAC
t
F
t
R
Low
=Don’tCare
Bit23=MSB
Bit0=LSB
t
11
t
12
t
13
TIMING CHARACTERISTICS For Figure 2 to Figure 3
(1) (2) (3)
DAC8234
www.ti.com ........................................................................................................................................... SBAS464A – AUGUST 2009 – REVISED SEPTEMBER 2009
Figure 3. SPI Timing for Readback Operation in Stand-Alone Mode
At T
A
= – 40 ° C to +105 ° C, unless otherwise noted.
2.7V ≤ DV
DD
≤ 5.5V, 2.7V ≤ DV
DD
≤ 3.6V, 3.6V < DV
DD
≤ 5.5V,
IOV
DD
= 1.8V 2.7V ≤ IOV
DD
≤ DV
DD
2.7V ≤ IOV
DD
≤ DV
DD
PARAMETER MIN MAX MIN MAX MIN MAX UNIT
f
SCLK
Clock frequency 15 20 25 MHz
t
1
SCLK cycle time 66 50 40 ns
t
2
SCLK high time 33 25 20 ns
t
3
SCLK low time 33 25 20 ns
t
4
CS falling edge to SCLK falling edge
(4)
25 22 17 ns
t
5
Input data setup time 5 5 5 ns
t
6
Input data hold time 5 5 5 ns
t
7
SCLK falling edge to CS rising edge 15 12 10 ns
t
8
CS high time 60 50 30 ns
t
9
CS rising edge to LDAC falling edge 30 25 20 ns
t
10
LDAC pulse width 25 20 15 ns
t
11
SDO data valid from SCLK rising edge 25 20 15 ns
SDO data hold time from SCLK falling
t
12
30 25 20 ns
edge
t
13
SDO data valid from CS falling edge 20 17 12 ns
RST pulse width 25 20 15 ns
(1) Specified by design and characterization.
(2) Sample tested during the initial release and after any redesign or process changes that may affect these parameters.
(3) All input signals are specified with t
R
= t
F
= 2ns (10% to 90% of IOV
DD
) and timed from a voltage level of IOV
DD
/2.
(4) The first SCLK edge after CS goes low must be a falling edge.
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