Datasheet

t
8
CS
SCLK
SDI
BIT23(N)
BIT22(N) BIT0(N) BIT23(N+1)
BIT23(N) BIT0(N)
Low
BIT0(N+1)
SDO
LDAC
t
4
t
1
t
2
t
3
t
F
t
R
t
5
t
6
t
7
Case3:Daisy-Chainmode, tiedlowLDAC .
High
LDAC
=Don’tCare
Bit23=MSB
Bit0=LSB
t
11
t
12
CS
SCLK
SDI
BIT23(N)
BIT22(N) BIT0(N) BIT23(N+1)
BIT23(N) BIT0(N)
BIT0(N+1)
SDO
t
1
t
2
t
3
t
F
t
R
t
7
Case4:Daisy-Chainmode, active.LDAC
t
11
t
12
InputDataRegisterand
DACLatchUpdated
(1)
InputDataRegister Updated
butDACLatchisNotUpdated
t
5
t
6
t
5
t
6
t
8
t
4
DACLatchUpdated
t
9
t
10
DAC8234
SBAS464A – AUGUST 2009 – REVISED SEPTEMBER 2009 ........................................................................................................................................... www.ti.com
Figure 2. SPI Timing for Daisy-Chain Mode
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