Datasheet

DAC8218
www.ti.com
SBAS460A MAY 2009REVISED DECEMBER 2009
ELECTRICAL CHARACTERISTICS: Single-Supply
All specifications at T
A
= T
MIN
to T
MAX
, AV
DD
= +32V, AV
SS
= 0V, IOV
DD
= DV
DD
= +5V, REF-A and REF-B = +5V, gain = 6,
AGND-x = DGND = 0V, data format = straight binary, and OFFSET-A = OFFSET-B = AGND, unless otherwise noted.
DAC8218
PARAMETER CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE
(1)
Resolution 14 Bits
Linearity error Measured by line passing through codes 0040h and 3FFFh ±1 LSB
Differential linearity error Measured by line passing through codes 0040h and 3FFFh ±1 LSB
T
A
= +25°C, before user calibration, gain = 6, code = 0040h ±2.5 LSB
Unipolar zero error T
A
= +25°C, before user calibration, gain = 4, code = 0040h ±4 LSB
T
A
= +25°C, after user calib., gain = 4 or 6, code = 0040h ±1 LSB
Unipolar zero error TC Gain = 4 or 6, code = 0040h ±0.5 ±3 ppm FSR/°C
T
A
= +25°C, gain = 6 ±2.5 LSB
Gain error
T
A
= +25°C, gain = 4 ±4 LSB
Gain error TC Gain = 4 or 6 ±1 ±3 ppm FSR/°C
T
A
= +25°C, before user calibration, gain = 6, code = 3FFFh ±2.5 LSB
Full-scale error T
A
= +25°C, before user calibration, gain = 4, code = 3FFFh ±4 LSB
T
A
= +25°C, after user calib., gain = 4 or 6, code = 3FFFh ±1 LSB
Full-scale error TC Gain = 4 or 6, code = 3FFFh ±0.5 ±3 ppm FSR/°C
Measured channel at code = 2000h, full-scale change on any
DC crosstalk
(2)
0.05 LSB
other channel
ANALOG OUTPUT (V
OUT
-0 to V
OUT
-7)
(3)
V
REF
= +5V 0 +30 V
Voltage output
(4)
V
REF
= +1.5V 0 +9 V
Output impedance Code = 2000h 0.5
Short-circuit current
(5)
±8 mA
Load current See Figure 84 and Figure 85 ±3 mA
T
A
= +25°C, device operating for 500 hours, full-scale output 3.4 ppm of FSR
Output drift vs time
T
A
= +25°C, device operating for 1000 hours, full-scale output 4.3 ppm of FSR
Capacitive load stability 500 pF
To 0.03% of FSR, C
L
= 200pF, R
L
= 10k, code from 0040h to
10 μs
3FFFh and 3FFFh to 0040h
To 1 LSB, C
L
= 200pF, R
L
= 10k, code from 0040h to 3FFFh
Settling time 15 μs
and 3FFFh to 0040h
To 1 LSB, C
L
= 200pF, R
L
= 10k, code from 1FC0h to 2040h
6 μs
and 2040h to 1FC0h
Slew rate
(6)
6 V/μs
Power-on delay
(7)
From IOV
DD
+1.8V and DV
DD
+2.7V to CS low 200 μs
Power-down recovery time 90 μs
Digital-to-analog glitch
(8)
Code from 1FFFh to 2000h and 2000h to 1FFFh 4 nV-s
Glitch impulse peak amplitude Code from 1FFFh to 2000h and 2000h to 1FFFh 5 mV
Channel-to-channel isolation
(9)
V
REF
= 4V
PP
, f = 1kHz 88 dB
(1) Gain = 4 and TC specified by design and characterization.
(2) The DAC outputs are buffered by op amps that share common AV
DD
and AV
SS
power supplies. DC crosstalk indicates how much dc
change in one or more channel outputs may occur when the dc load current changes in one channel (because of an update). With
high-impedance loads, the effect is virtually immeasurable. Multiple AV
DD
and AV
SS
terminals are provided to minimize dc crosstalk.
(3) Specified by design.
(4) The analog output range of V
OUT
-0 to V
OUT
-7 is equal to (6 × V
REF
) for gain = 6. The maximum value of the analog output must not be
greater than (AV
DD
– 0.5V). All specifications are for a +32V power supply and a 0V to +30V output, unless otherwise noted.
(5) When the output current is greater than the specification, the current is clamped at the specified maximum value.
(6) Slew rate is measured from 10% to 90% of the transition when the output changes from 0 to full-scale.
(7) Power-on delay is defined as the time from when the supply voltages reach the specified conditions to when CS goes low, for valid
digital communication.
(8) Digital-to-analog glitch is defined as the amount of energy injected into the analog output at the major code transition. It is specified as
the area of the glitch in nV-s. It is measured by toggling the DAC register data between 1FFFh and 2000h in straight binary format.
(9) Channel-to-channel isolation refers to the ratio of the signal amplitude at the output of one DAC channel to the amplitude of the
sinusoidal signal on the reference input of another DAC channel. It is expressed in dB and measured at midscale.
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