Datasheet

DAC8218
www.ti.com SBAS460A –MAY 2009–REVISED DECEMBER 2009
ELECTRICAL CHARACTERISTICS: Dual-Supply (continued)
All specifications at T
A
= T
MIN
to T
MAX
, AV
DD
= +16.5V, AV
SS
= –16.5V, IOV
DD
= DV
DD
= +5V, REF-A and REF-B = +5V,
gain = 6, AGND-x = DGND = 0V, data format = straight binary, and Offset DAC A and Offset DAC B are at default values
(1)
,
unless otherwise noted.
DAC8218
PARAMETER CONDITIONS MIN TYP MAX UNIT
OFFSET DAC OUTPUT
(15) (16)
Voltage output V
REF
= +5V 0 5 V
Full-scale error T
A
= +25°C ±1 LSB
Zero-code error T
A
= +25°C ±0.5 LSB
Linearity error ±1.5 LSB
Differential linearity error ±1 LSB
ANALOG MONITOR PIN (V
MON
)
Output impedance
(17)
T
A
= +25°C 2 kΩ
Three-state leakage current 100 nA
AUXILIARY ANALOG INPUT
Input range AV
SS
AV
DD
V
Input impedance
T
A
= +25°C 2 kΩ
(AIN-x to V
MON
)
Input capacitance
(15)
4 pF
Input leakage current 30 nA
REFERENCE INPUT
Reference input voltage range
(18)
1.0 5.5 V
Reference input dc impedance 10 MΩ
Reference input capacitance
(15)
10 pF
DIGITAL INPUT
(15)
IOV
DD
= +4.5V to +5.5V 3.8 0.3 + IOV
DD
V
High-level input voltage, V
IH
IOV
DD
= +2.7V to +3.3V 2.3 0.3 + IOV
DD
V
IOV
DD
= +1.7V to 2.0V 1.5 0.3 + IOV
DD
V
IOV
DD
= +4.5V to +5.5V –0.3 0.8 V
Low-level input voltage, V
IL
IOV
DD
= +2.7V to +3.3V –0.3 0.6 V
IOV
DD
= +1.7V to 2.0V –0.3 0.3 V
CLR, LDAC, RST, CS, and SDI ±1 μA
Input current
USB/BTC, RSTSEL, and GPIO-n ±5 μA
CLR, LDAC, RST, CS, and SDI 5 pF
Input capacitance USB/BTC and RSTSEL 12 pF
GPIO-n 14 pF
DIGITAL OUTPUT
(15)
IOV
DD
= +2.7V to +5.5V, sourcing 1mA IOV
DD
– 0.4 IOV
DD
V
High-level output voltage, V
OH
(SDO)
IOV
DD
= +1.8V, sourcing 200μA 1.6 IOV
DD
V
IOV
DD
= +2.7V to +5.5V, sinking 1mA 0 0.4 V
Low-level output voltage, V
OL
(SDO)
IOV
DD
= +1.8V, sinking 200μA 0 0.2 V
GPIO-n output voltage low, V
OL
1mA sink from IOV
DD
0.15 V
GPIO-n output voltage high, V
OH
10kΩ pull-up resistor to IOV
DD
0.99 × IOV
DD
V
High-impedance leakage current SDO and GPIO-n ±5 μA
SDO 5 pF
High-impedance output
capacitance
GPIO-n 14 pF
(15) Specified by design.
(16) Offset DAC A and Offset DAC B are trimmed in manufacturing to minimize the error for symmetrical output. The default value may vary
no more than ±3 LSB from the nominal number listed in Table 7. The Offset DAC pins are not intended to drive an external load, and
must not be connected during dual-supply operation.
(17) 8kΩ when V
MON
is connected to Reference Buffer A or B, and 4kΩ when V
MON
is connected to Offset DAC-A or -B.
(18) Reference input voltage ≤ DV
DD
.
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