Datasheet

DAC8218
SBAS460A –MAY 2009–REVISED DECEMBER 2009 www.ti.com
Table 10. Register Map
ADDRESS BITS DATA BITS
A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3:D0 REGISTER
Configuration
0 0 0 0 0 A/B LD RST PD-A PD-B SCE X GAIN-A GAIN-B DSDO NOP W2 X
(1)
Register
0 0 0 0 1 Analog Monitor Select X
(1)
Monitor Register
0 0 0 1 0 GPIO-2 GPIO-1 GPIO-0 X
(1)
GPIO Register
Offset DAC-A
0 0 0 1 1 OS13:OS0, X, X
(2)
Data
Offset DAC-B
0 0 1 0 0 OS13:OS0, X, X
(2)
Data
0 0 1 0 1 Reserved
(3)
Reserved
0 0 1 1 0 SLEEP Reserved
(3)
SPI MODE
0 0 1 1 1 DB13:DB0, X, X Broadcast
0 1 0 0 0 DB13:DB0, X, X DAC-0
0 1 0 0 1 DB13:DB0, X, X DAC-1
0 1 0 1 0 DB13:DB0, X, X DAC-2
0 1 0 1 1 DB13:DB0, X, X DAC-3
0 1 1 0 0 DB13:DB0, X, X DAC-4
0 1 1 0 1 DB13:DB0, X, X DAC-5
0 1 1 1 0 DB13:DB0, X, X DAC-6
0 1 1 1 1 DB13:DB0, X, X DAC-7
1 0 0 0 0 Z13:Z0, X, X, default = 0 (0000h), twos complement Zero Register-0
1 1 0 0 0 G13:G0, X, X, default = 8192 (2000h), straight binary Gain Register-0
1 0 0 0 1 Z13:Z0, X, X, default = 0 (0000h), twos complement Zero Register-1
1 1 0 0 1 G13:G0, X, X, default = 8192 (2000h), straight binary Gain Register-1
1 0 0 1 0 Z13:Z0, X, X, default = 0 (0000h), twos complement Zero Register-2
1 1 0 1 0 G13:G0, X, X, default = 8192 (2000h), straight binary Gain Register-2
1 0 0 1 1 Z13:Z0, X, X, default = 0 (0000h), twos complement Zero Register-3
1 1 0 1 1 G13:G0, X, X, default = 8192 (2000h), straight binary Gain Register-3
1 0 1 0 0 Z13:Z0, X, X, default = 0 (0000h), twos complement Zero Register-4
1 1 1 0 0 G13:G0, X, X, default = 8192 (2000h), straight binary Gain Register-4
1 0 1 0 1 Z13:Z0, X, X, default = 0 (0000h), twos complement Zero Register-5
1 1 1 0 1 G13:G0, X, X, default = 8192 (2000h), straight binary Gain Register-5
1 0 1 1 0 Z13:Z0, X, X, default = 0 (0000h), twos complement Zero Register-6
1 1 1 1 0 G13:G0, X, X, default = 8192 (2000h), straight binary Gain Register-6
1 0 1 1 1 Z13:Z0, X, X, default = 0 (0000h), twos complement Zero Register-7
1 1 1 1 1 G13:G0, X, X, default = 8192 (2000h), straight binary Gain Register-7
(1) X = don't care—writing to this bit has no effect; reading the bit returns '0'.
(2) Table 7 lists the default values for a dual power supply. Offset DAC A and Offset DAC B are trimmed in manufacturing to minimize the
error for symmetrical output. The default value may vary no more than ±3 LSB from the nominal number listed in Table 7. For a single
power supply, the Offset DACs are turned off.
(3) Writing to a reserved bit has no effect; reading the bit returns '0'.
48 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): DAC8218