Datasheet

DAC8218
SBAS460A –MAY 2009–REVISED DECEMBER 2009 www.ti.com
MONITOR OUTPUT PIN (V
MON
)
The V
MON
pin is the channel monitor output. It can be either high-impedance or monitor any one of the DAC
outputs, auxiliary analog inputs, offset DAC outputs, or reference buffer outputs. The channel monitor function
consists of an analog multiplexer addressed via the serial interface, allowing any channel output, reference buffer
output, auxiliary analog inputs, or offset DAC output to be routed to the V
MON
pin for monitoring using an external
ADC. The monitor function is controlled by the Monitor Register, which allows the monitor output to be enabled
or disabled. When disabled, the monitor output is high-impedance; therefore, several monitor outputs may be
connected in parallel with only one enabled at a time.
Note that the multiplexer is implemented as a series of analog switches. Care should be taken to ensure the
maximum current from the V
MON
pin must not be greater than the given specification because this could
conceivably cause a large amount of current to flow from the input of the multiplexer (that is, from V
OUT
-X) to the
output of the multiplexer (V
MON
). Refer to the Monitor Register section and Table 12 for more details.
ANALOG INPUT PINS (AIN-0 and AIN-1)
Pins AIN-0 and AIN-1 are two analog inputs that directly connect to the analog mux of the analog monitor output.
When AIN-0 or AIN-1 is accessed, it is routed via the mux to the V
MON
pin. Thus, one external ADC channel can
monitor eight DACs plus two extra external analog signals, AIN-0 and AIN-1.
POWER-DOWN MODE
The DAC8218 is implemented with a power-down function to reduce power consumption. Either the entire device
or each individual group can be put into power-down mode. If the proper power-down bit (PD-x) in the
Configuration Register is set to '1', the individual group is put into power down mode. During power-down mode,
the analog outputs (V
OUT
-0 to V
OUT
-7) connect to AGND-X through an internal 15kΩ resistor, and the output
buffer is in Hi-Z status. When the entire device is in power-down, the bus interface remains active in order to
continue communication and receive commands from the host controller, but all other circuits are powered down.
The host controller can wake the device from power-down mode and return to normal operation by clearing the
PD-x bit; it takes 200μs or less for recovery to complete.
POWER-ON RESET SEQUENCING
The DAC8218 permanently latches the status of some of the digital pins at power-on. These digital levels should
be well-defined before or while the digital supply voltages are applied. Therefore, it is advised to have a pull up
resistor to IOV
DD
for the digital initialization pins (LDAC, CLR, RST, CS, and RSTSEL) to ensure that these levels
are set correctly while the digital supplies are raised.
For proper power-on initialization of the device, IOV
DD
and the digital pins must be applied before or at the same
time as DV
DD
. If possible, it is preferred that IOV
DD
and DV
DD
can be connected together in order to simplify the
supply sequencing requirements. Pull-up resistors should go to either supply. AV
DD
should be applied after the
digital supplies (IOV
DD
and DV
DD
) and digital initialization pins (LDAC, CLR, RST, CS, and RSTSEL). AV
SS
can
be applied at the same time as or after AV
DD
. The REF-x pins must be applied last.
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