Datasheet

DAC8218
www.ti.com SBAS460A –MAY 2009–REVISED DECEMBER 2009
TIMING CHARACTERISTICS: IOV
DD
= +1.8V
(1)(2)(3)(4)
At –40°C to +105°C, DV
DD
= +3V/+5V, and IOV
DD
= +1.8V, unless otherwise noted.
PARAMETER MIN MAX UNIT
f
SCLK
Clock frequency 16.6 MHz
t
1
SCLK cycle time 60 ns
t
2
SCLK high time 28 ns
t
3
SCLK low time 7 ns
t
4
CS falling edge to SCLK falling edge setup time 28 ns
t
5
SDI setup time before falling edge of SCLK 10 ns
t
6
SDI hold time after falling edge of SCLK 5 ns
t
7
SCLK falling edge to CS rising edge 10 ns
t
8
CS high time 28 ns
t
9
CS rising edge to LDAC falling edge 5 ns
t
10
LDAC pulse duration 10 ns
t
11
Delay from SCLK rising edge to SDO valid 3 25 ns
t
12
Delay from CS rising edge to SDO Hi-Z 15 ns
t
13
Delay from CS falling edge to SDO valid 23 ns
t
14
SDI to SDO delay during sleep mode 2 25 ns
(1) Specified by design. Not production tested.
(2) Sample tested during the initial release and after any redesign or process changes that may affect these parameters.
(3) All input signals are specified with t
R
= t
F
= 6ns (10% to 90% of IOV
DD
) and timed from a voltage level of IOV
DD
/2.
(4) SDO loaded with 10Ω series resistance and 10pF load capacitance for SDO timing specifications.
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): DAC8218