Datasheet
DAC8218
SBAS460A –MAY 2009–REVISED DECEMBER 2009
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TIMING CHARACTERISTICS: IOV
DD
= +5V
(1)(2)(3)(4)
At –40°C to +105°C, DV
DD
= +5V, and IOV
DD
= +5V, unless otherwise noted.
PARAMETER MIN MAX UNIT
f
SCLK
Clock frequency 50 MHz
t
1
SCLK cycle time 20 ns
t
2
SCLK high time 10 ns
t
3
SCLK low time 7 ns
t
4
CS falling edge to SCLK falling edge setup time 8 ns
t
5
SDI setup time before falling edge of SCLK 5 ns
t
6
SDI hold time after falling edge of SCLK 5 ns
t
7
SCLK falling edge to CS rising edge 5 ns
t
8
CS high time 10 ns
t
9
CS rising edge to LDAC falling edge 5 ns
t
10
LDAC pulse duration 10 ns
t
11
Delay from SCLK rising edge to SDO valid 3 8 ns
t
12
Delay from CS rising edge to SDO Hi-Z 5 ns
t
13
Delay from CS falling edge to SDO valid 6 ns
t
14
SDI to SDO delay during sleep mode 2 5 ns
(1) Specified by design. Not production tested.
(2) Sample tested during the initial release and after any redesign or process changes that may affect these parameters.
(3) All input signals are specified with t
R
= t
F
= 2ns (10% to 90% of IOV
DD
) and timed from a voltage level of IOV
DD
/2.
(4) SDO loaded with 10Ω series resistance and 10pF load capacitance for SDO timing specifications.
BLANKSPACE
TIMING CHARACTERISTICS: IOV
DD
= +3V
(1)(2)(3)(4)
At –40°C to +105°C, DV
DD
= +3V/+5V, and IOV
DD
= +3V, unless otherwise noted.
PARAMETER MIN MAX UNIT
f
SCLK
Clock frequency 25 MHz
t
1
SCLK cycle time 40 ns
t
2
SCLK high time 19 ns
t
3
SCLK low time 7 ns
t
4
CS falling edge to SCLK falling edge setup time 15 ns
t
5
SDI setup time before falling edge of SCLK 5 ns
t
6
SDI hold time after falling edge of SCLK 5 ns
t
7
SCLK falling edge to CS rising edge 10 ns
t
8
CS high time 19 ns
t
9
CS rising edge to LDAC falling edge 5 ns
t
10
LDAC pulse duration 10 ns
t
11
Delay from SCLK rising edge to SDO valid 3 15 ns
t
12
Delay from CS rising edge to SDO Hi-Z 7 ns
t
13
Delay from CS falling edge to SDO valid 10 ns
t
14
SDI to SDO delay during sleep mode 2 10 ns
(1) Specified by design. Not production tested.
(2) Sample tested during the initial release and after any redesign or process changes that may affect these parameters.
(3) All input signals are specified with t
R
= t
F
= 3ns (10% to 90% of IOV
DD
) and timed from a voltage level of IOV
DD
/2.
(4) SDO loaded with 10Ω series resistance and 10pF load capacitance for SDO timing specifications.
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