Datasheet

t
8
CS
SCLK
SDI
BIT23(N)
BIT22(N) BIT0(N) BIT23(N+1)
BIT23(N) BIT0(N)
Low
BIT0(N+1)
SDO
LDAC
Ifthecorrectionengineisoff,theDAClatchisreloadedimmediatelyaftertheDACDataRegisterisupdated.NOTE:(1)
TheDAClatchisupdatedwhen goeslow.Theproperdataareloadedifthet timingrequirementissatisfied.
Otherwise,invaliddataareloaded.
9
LDAC
NOTE:(2)
t
4
t
1
t
2
t
5
t
6
t
7
Case3:Daisy-ChainMode:Updatewithout pin; pintiedtologiclow.LDAC LDAC
High
LDAC
t
9
t
10
=Don’tCare
Bit23=MSB
Bit0=LSB
t
11
t
8
CS
SCLK
InputDataRegisterUpdated,
butDACLatchisNotUpdated
SDI
BIT23(N)
BIT22(N) BIT0(N) BIT23(N+1)
BIT23(N) BIT0(N)
BIT0(N+1)
SDO
t
4
t
1
t
2
t
5
t
6
t
7
Case4:Daisy-ChainMode:Updatewith pin.LDAC
t
11
t
14
DACLatchUpdated
(2)
InputDataRegisterand
DACLatchUpdated
WhenCorrectionCompletes
(1)
DB23 DB0
Case5:Daisy-ChainMode:Sleeping.
CS
SCLK
SDI
FirstWord LastWord
DB23 DB0
DB23 DB0
SDO
DB23 DB0
t
12
t
12
Hi-Z
Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z
t
13
t
13
t
3
t
3
Hi-Z
DAC8218
SBAS460A –MAY 2009–REVISED DECEMBER 2009 www.ti.com
TIMING DIAGRAMS (continued)
Figure 3. SPI Timing for Daisy-Chain Mode
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