Datasheet

t
8
CS
SCLK
InputDataRegisterand
DACLatchUpdated
WhenCorrectionCompletes
(1)
DACLatchUpdated
(2)
SDI
BIT23(MSB)
BIT23(MSB)
BIT22 BIT1
Low
BIT0
LDAC
Ifthecorrectionengineisoff,theDAClatchisreloadedimmediatelyaftertheDACDataRegisterisupdated.NOTE:(1)
TheDAClatchisupdatedwhen goeslow,aslongasthetimingrequirementoft issatisfied.
9
LDAC
NOTE:(2)
t
4
t
1
t
2
t
5
t
6
t
7
Case1:Standalonemode:Updatewithout pin; tiedtologiclowLDAC LDAC pin .
t
8
CS
SCLK
InputDataRegisterUpdated,
butDACLatchisNot Updated
SDI
BIT22 BIT1
High
BIT0
LDAC
t
4
t
1
t
2
t
5
t
6
t
7
t
9
Case2:Standalonemode:Updatewith pin.LDAC
t
10
=Don’tCare
Bit23=MSB
Bit0=LSB
t
3
t
3
DAC8218
www.ti.com SBAS460A –MAY 2009–REVISED DECEMBER 2009
TIMING DIAGRAMS
Figure 2. SPI Timing for Standalone Mode
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