Datasheet

DAC8218
SBAS460A –MAY 2009–REVISED DECEMBER 2009 www.ti.com
PIN DESCRIPTIONS (continued)
PIN NO.
PIN
NAME
QFN-48 TQFP-64 I/O DESCRIPTION
DV
DD
17 24 I Digital power supply
DGND 20 25 I Digital ground
DGND 22 28 I Digital ground
General-purpose digital input/output 1. This pin is a bidirectional digital input/output, open-drain and
GPIO-1 23 29 I/O
requires an external resistor. See the GPIO Pins section for details.
General-purpose digital input/output 0. This pin is a bidirectional digital input/output, open-drain and
GPIO-0 24 30 I/O
requires an external resistor. See the GPIO Pins section for details.
AV
SS
26 37 I Negative analog power supply
V
OUT
-7 27 38 O DAC-7 output
OFFSET DAC-B analog output. Must be connected to AGND-B during single-supply operation
OFFSET-B 28 39 O
(AV
SS
= 0V).
AGND-B 29 40 I Group B
(1)
analog ground and the ground of REF-B. This pin must be tied to AGND-A and DGND.
AGND-B 30 41 I Group B analog ground and the ground of REF-B. This pin must be tied to AGND-A and DGND.
V
OUT
-6 31 42 O DAC-6 output
V
OUT
-5 32 43 O DAC-5 output
REF-B 33 44 I Group B reference input
V
OUT
-4 34 45 O DAC-4 output
AIN-1 35 46 I Auxiliary analog input 1, directly routed to the analog mux
AV
DD
36 48 I Positive analog power supply
Data format selection of Input DAC data and Offset DAC data. Data are in straight binary format
USB/BTC 37 50 I when connected to DGND or in twos complement format when connected to IOV
DD
. The command
data are always in straight binary format. Refer to Input Data Format section for details.
Output reset selection. Selects the output voltage on the V
OUT
pin after power-on or hardware reset.
RSTSEL 38 51 I
Refer to the Power-On Reset section for details.
DGND 40 54 I Digital ground
IOV
DD
41 55 I Interface power
DV
DD
42 56 I Digital power supply
SCLK 43 57 I SPI bus serial clock input
SPI bus chip select input (active low). Data are not clocked into SDI unless CS is low. When CS is
CS 44 58 I
high, SDO is in a high-impedance state and the SCLK and SDI signals are blocked from the device.
SDI 45 59 I SPI bus serial data input
SPI bus serial data output.
When the DSDO bit = '0', the SDO pin works as an output in normal operation.
SDO 46 61 O
When the DSDO bit = '1', SDO is always in a Hi-Z state, regardless of the CS pin status. Refer to
the Timing Diagrams section for details.
Load DAC latch control input (active low). When LDAC is low, the DAC latch is transparent and the
contents of the DAC Data Register are transferred to it. The DAC output changes to the
corresponding level simultaneously when the DAC latch is updated. See the Updating the DAC
LDAC 47 62 I
Outputs section for details. If asynchronous mode is desired, LDAC must be permanently tied low
before power is applied to the device. If synchronous mode is desired, LDAC must be logic high
during power-on.
Wake-up input (active low). Restores the SPI from sleep to normal operation. See the Daisy-Chain
WAKEUP 48 63 I
Operation section for details.
2, 13,
15-18, 22,
16, 18, 19, 23, 26, 27,
NC — Not connected
21, 25, 39 31-36, 47,
49, 52, 53,
60, 64
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