Datasheet

DAC8164 EVM: InstallshuntonJMP 4
DAC8165 EVM: DonotinstallshuntonJMP 4
3.2 Host Processor Interface
3.3 EVM Stacking
EVM Operation
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Table 2. Factory Default Jumper Setting (continued)
Reference Jumper Function
JMP15 1-2 DAC output (V
OUT
A) is routed to the noninverting input of U2 operational amplifier.
JMP16 1-2 U2 output is monitored from J4A-5.
JMP17 1-2 Digital supply IOV
DD
for the DAC8164/65 is +5 VD.
JMP18 2-3 FSX signal from J2A-7 is used for frame synchronization, SYNC, signal.
J4A 1-2 DAC output (V
OUT
A) is connected to the noninverting input of the output operational amplifier, U2.
Figure 9. DAC8164/65EVM Default Jumper Configuration
The host processor basically drives the DAC; so, the DACs proper operation depends on the successful
configuration between the host processor and the EVM board. In addition, a properly written code is also
required to operate the DAC.
A custom cable can be made specific to the host interface platform. The EVM allows interface to the host
processor through J2A header connector for the serial control signals and the serial data input. The output
can be monitored through the J4A header connector.
An interface adapter board is also available for a specific TI DSP starter kit as well as an MSP430-based
microprocessor as mentioned in section 1 of this manual. Using the interface board alleviates the tedious
task of building customized cables and allows easy configuration of a simple evaluation system.
The DAC8164/65 interfaces with any host processor capable of handling SPI protocols or the TI DSP. For
more information regarding the DAC8164 or the DAC8165 data interface, see the data sheet, (SBAS410
or SBAS409 ), respectively.
The stacking of EVMs is possible if a user needs to evaluate two DAC8164/65 devices to yield a total of
up to eight- (DAC8164/65) channel outputs. A maximum of two EVMs are allowed because the output
terminal, J4, dictates the number of DAC channels that can be connected without output bus contention.
Table 3 shows how the DAC output channels are mapped into the output terminal, J4, with respect to the
jumper position of JMP11, JMP12, JMP13, and JMP14.
DAC8164/65 Evaluation Module10 SLAU256 August 2008
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