Datasheet

11
®
DAC813
FIGURE 9. Interfacing Multiple DAC813s to an 8-Bit Bus.
Base
Address
Decoder
WR
A
A
15
4
A
A
A
2
1
0
Microcomputer
A
3
74LS138
C
B
A
G
G
G
2A
2B
1
DAC813
(1)
DAC813
(2)
WR
LDAC
LLSB
LMSB
DAC813
(4)
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
15
14
13
12
11
10
9
7
3
2
1
4
6
5
CS
WR
LDAC
LLSB
LMSB
WR
LDAC
LLSB
LMSB
ADDRESS BUS
A3 A2 A1 A0 OPERATION
0 0 0 0 Load 8 LSB – D/A #1
0 0 0 1 Load 4 MSB – D/A #1
0 0 1 0 Load 8 LSB – D/A #2
0 0 1 1 Load 4 MSB – D/A #2
0 1 0 0 Load 8 LSB – D/A #3
0 1 0 1 Load 4 MSB – D/A #3
0 1 1 0 Load 8 LSB – D/A #4
0 1 1 1 Load 4 MSB – D/A #4
1 X X X Load D/A Latch—All D/A