Datasheet
®
10
DAC813
INTERFACING MULTIPLE
DAC813s IN 8-BIT SYSTEMS
Many applications, such as automatic test systems, require
that the outputs of several D/A converters be updated simul-
taneously. The interface shown in Figure 9 uses a 74LSB138
decoder to decode a set of eight adjacent addresses to load
the input latches of four DAC813s. The example uses a
right-justified data format.
A ninth address using A3 causes all DAC813s to be updated
simultaneously. If a certain DAC813 is always loaded last
(for instance, D/A #4), A3 is not needed, saving 8 address
spaces for other uses. Incorporate A3 into the base address
decoder, remove the inverter, connect the common LDAC
line to LLSB of D/A #4, and connect D1 of the 74LS138 to
+5V.
12- AND 16-BIT MICROCOMPUTER INTERFACE
For this application the input latch enable lines, LMSB and
LLSB, are tied low, causing the latches to be transparent.
The D/A latch, and therefore DAC813, is selected by the
address decoder and strobed by WR.
Be sure and read the CAUTION statement in the LOGIC
INPUT COMPATIBILITY section.
FIGURE 6. Output Amplifier Voltage Range Scaling Circuit.
25kΩ
25kΩ
24.9kΩ
9
3
2
4
BPO
20V
20V
V
OUT
±5V
6
200 pot or
100 fixed
Ω
Ω
±5V
RANGE
25kΩ
25kΩ
24.9kΩ
9
3
2
4
BPO
20V
20V
V
OUT
±10V
V
REF OUT
6
200 pot or
100 fixed
Ω
Ω
±10V
RANGE
25kΩ
25kΩ
24.9kΩ
9
3
2
4
BPO
20V
20V
V
OUT
0 to +10V
0 TO +10V
RANGE
NC
NC
I
DAC
I
DAC
I
DAC
5
5
V
REF OUT
5
ACOM
ACOM
ACOM
FIGURE 8. Right-Justified Data Bus Interface.
D0
D8
D1
D9
D2
D10
D3
D11
D4
D5
D6
D7
17
25
18
26
19
27
20
28
21
22
23
24
DB0
DB1
DB2
DB3
Reset Circuitry
DB4
DB5
DB6
DB7
WR
A
A
1
0
Microcomputer
DAC813
Base
Address
Decoder
A
A
15
2
11
12
14
15
13
WR
LDAC
LMSB
LLSB
Reset
X X X X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Right-Justified
FIGURE 7. 12-Bit Data Format for 8-Bit Systems.