Datasheet

4
®
DAC8043
WRITE CYCLE TIMING DIAGRAM
SRI
Bit 1
MSB
(1)
Bit 2 Bit 11
Bit 12
LSB
t
DH
t
CH
t
CL
1
CLK INPUT
LD
Load Serial Data
Into Input Register
Load Input Register's
Data Into DAC Register
t
DS
2
11
NOTE: (1) Data loaded MSB first.
t
ASB
t
LD