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SYNC Interrupt (Stand-Alone Mode)
Daisy-Chain
t
CSS
t
CH
t
DS
t
DH
t
DDS
t
CC
t
CST
t
SH
t
C
SCLK
SDIN
DB15
(N)
DB0
(N)
DB15
(N)
DB0
(N)
DB15
(N+1)
DB0
(N+1)
SDO
SYNC
DAC7811
SBAS337C – APRIL 2005 – REVISED JULY 2007
In a normal write sequence, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is
updated on the 16th falling edge. However, if SYNC is brought high before the 16th falling edge, this acts as an
interrupt to the write sequence. The shift register is reset and the write sequence is seen as invalid. Neither an
update of the DAC register contents nor a change in the operating mode occurs.
The DAC7811 powers up in the daisy-chain mode which must be used when two or more devices are connected
in tandem. The SCLK and SYNC signals are shared across all devices while the SDO output of the first device
connects to the SDIN input of the following device, and so forth. In this configuration 16 SCLK cycles for each
DAC7811 in the chain are required. Please refer to the timing diagram of Figure 28 .
For n devices in a daisy-chain configuration, 16 n SCLK cycles are required to shift in the entire input data
stream. After 16 n active SCLK edges are received following a falling SYNC, the data stream becomes complete,
and SYNC can brought high to update n devices simultaneously.
When SYNC is brought high, each device will execute the function defined by the four DAC control bits C3-C0 in
its input shift register. For example, C3-C0 must be 0001 for each DAC in the chain that is to be updated with
new data, and C3-C0 must be 0000 for each DAC in the chain whose contents are to remain unchanged.
A continuous stream containing the exact number of SCLK cycles may be sent first while the SYNC signal is
held low, and then raise SYNC at a later time. Nothing happens until the rising edge of SYNC, and then each
DAC7811 in the chain will execute the function defined by the four DAC control bits C3-C0 in its input shift
register.
Figure 28. DAC7811 Timing Diagram
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