Datasheet

DAC7800, 7801, 7802
5
SBAS005A
www.ti.com
LOGIC TRUTH TABLE
BLOCK DIAGRAM PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
AGND A
CS
DB0
DB1
DB2
DB3
DB4
DB5
DGND
AGND B
I
R
V
V
UPD
WR
CLR
A1
A0
DB7
DB6
OUT A
FB A
REF A
FB B
REF B
DD
OUT B
DAC7801
I
R
V
DAC7801
CLR UPD CS WR A1 A0 FUNCTION
1 1 1 X X X No Data Transfer
1 1 X 1 X X No Data Transfer
0 X X X X X All Registers Cleared
1 1 0 0 0 0 DAC A LS Input Register Loaded with DB7 - DB0 (LSB)
1 1 0 0 0 1 DAC A MS Input Register Loaded with DB3 (MSB) - DB0
1 1 0 0 1 0 DAC B LS Input Register Loaded with DB7 - DB0 (LSB)
1 1 0 0 1 1 DAC B MS Input Register Loaded with DB3 (MSB) - DB0
1 0 1 0 X X DAC A, DAC B Registers Updated Simultaneously from Input Registers
1 0 0 0 X X DAC A, DAC B Registers are Transparent
X = Don’t care.
TIMING CHARACTERISTICS
V
DD
= +5V, V
REF A
= V
REF B
= +10V, T
A
= –40°C to +85°C.
PARAMETER MINIMUM
t
1
— Address Valid to Write Setup Time 10ns
t
2
— Address Valid to Write Hold Time 10ns
t
3
— Data Setup Time 30ns
t
4
— Data Hold Time 10ns
t
5
— Chip Select or Update to Write Setup Time 0ns
t
6
— Chip Select or Update to Write Hold Time 0ns
t
7
— Write Pulse Width 40ns
t
8
— Clear Pulse Width 40ns
A0–A1
CLR
t
2
t
1
t
8
WR
t
7
CS, UPD
t
6
t
4
t
3
DATA
t
5
5V
0V
5V
0V
5V
0V
5V
0V
5V
0V
NOTES: (1) All input signal rise and fall times are measured from 10% to 90%
of +5V. t
R
= t
F
= 5ns. (2) Timing measurement reference level is .
V
IH
+ V
IL
2
DAC A
I
AGND A
R
V
V
R
I
AGND B
OUT A
FB A
REF A
REF B
FB B
OUT B
20
V
DD
2
1
3
4
21
22
23
24
DAC A Register
4
8
DAC A
LS
Input
Reg
DAC A
MS
Input
Reg
Control Logic
DAC B
DAC B Register
4
8
12
DGND
DAC B
LS
Input
Reg
DAC B
MS
Input
Reg
19
16
15
5
18
17
UPD
A1
A0
CS
WR
CLR
DAC7801
14 6
DB7–DB0
12
12
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