Datasheet

DAC7800, 7801, 7802
4
SBAS005A
www.ti.com
DATA
CS
CLK
t
1
t
5
UPD A
UPD B
t
3
t
7
CLR
t
6
t
8
t
4
0V
5V
5V
5V
5V
0V
NOTES: (1) All input signal rise and fall times are measured from 10% to 90% of +5V. t = t = 5ns.
(2) Timing measurement reference level is
V + V
2
FR
IH IL
.
t
2
PARAMETER MINIMUM
t
1
— Data Setup Time 15ns
t
2
— Data Hold Time 15ns
t
3
— Chip Select to CLK, 15ns
Update, Data Setup Time
t
4
— Chip Select to CLK, 40ns
Update, Data Hold Time
t
5
— CLK Pulse Width 40ns
t
6
— Clear Pulse Width 40ns
t
7
— Update Pulse Width 40ns
t
8
— CLK Edge to UPD A 15ns
or UPD B
TIMING CHARACTERISTICS
V
DD
= +5V, V
REF A
= V
REF B
= +10V, T
A
= –40°C to +85°C.
Data In
Bit 0 Bit 23Bit 22Bit 21Bit 20Bit 19Bit 18Bit 17Bit 16Bit 15Bit 14Bit 13Bit 12Bit 11Bit 10Bit 9Bit 8Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1
LSB
DAC A
MSB
DAC A
LSB
DAC B
MSB
DAC B
DAC7800 Data Input Sequence
DAC7800 Digital Interface Block Diagram
24-Bit
Shift Register
DAC A Register
UPD A
Data In
CLK
UPD B
LSB MSB
DAC B Register
LSB MSB
Bit
23
Bit
12
Bit
11
Bit
0
CLK
DATA INPUT FORMAT
DAC7800 (Cont.)