Datasheet

16
®
DAC7744
FIGURE 1. DAC7744 Architecture.
FIGURE 2. Basic Single-Supply Operation of the DAC7744.
THEORY OF OPERATION
The DAC7744 is a quad voltage output, 16-bit digital-to-
analog converter (DAC). The architecture is an R-2R ladder
configuration with the three MSB’s segmented followed by
an operational amplifier that serves as a buffer. Each DAC
has its own R-2R ladder network, segmented MSBs and
output op amp (see Figure 1). The minimum voltage output
(zero scale) and maximum voltage output (full scale) are set
by the external voltage references (V
REF
L and V
REF
H, re-
spectively). The digital input is a 16-bit parallel word and
the DAC input registers offer a readback capability. The
converters can be powered from either a single +15V supply
or a dual ±15V supply. The device offers a reset function
which immediately sets all DAC output voltages and DAC
registers to mid-scale code 8000
H
or to zero scale, code
0000
H
. See Figures 2 and 3 for the basic operation of the
DAC7744.
R
2R
2R2R 2R 2R 2R 2R 2R 2R
V
REF
H
V
OUT
V
OUT
Sense
V
REF
H Sense
V
REF
L
V
REF
L Sense
R
F
DB15 (MSB)
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0 (LSB)
RSTSEL
RST
LOADDACS
R/W
A1
A0
CS
DGND
NC
NC
NC
NC
V
OUT
A Sense
V
OUT
A
V
REF
L AB Sense
V
REF
L AB
V
REF
H AB
V
REF
H AB Sense
V
OUT
B Sense
V
OUT
B
V
OUT
C Sense
V
OUT
C
V
REF
H CD Sense
V
REF
H CD
V
REF
L CD
V
REF
L CD Sense
V
OUT
D Sense
V
OUT
D
V
SS
AGND
V
CC
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
DAC7744
Reset DACs
Data
Bus
Address
Load DAC Registers
READ/WRITE
Chip Select
NC = No Connection
0V to +10V
0V to +10V
0V to +10V
0V to +10V
+10.000V
+10.000V
+15V
0.1µF
1µF
+5V
0.1µF
1µF
+
+