Datasheet

DAC7734
23
SBAS138A
www.ti.com
SYMBOL DESCRIPTION MIN MAX UNITS
t
DS
Data Valid to CLK Rising 10 ns
t
DH
Data Held Valid after CLK Rises 20 ns
t
CH
CLK HIGH 25 ns
t
CL
CLK LOW 25 ns
t
CSS
CS LOW to CLK Rising 15 ns
t
CSH
CLK HIGH to CS Rising 0 ns
t
LD1
LOAD HIGH to CLK Rising 10 ns
t
LD2
CLK Rising to LOAD LOW 30 ns
t
LDRW
LOAD LOW Time 30 ns
t
LDDL
LDAC LOW Time 40 ns
t
LDDH
LDAC HIGH Time 40 ns
t
SDO
SDO Propagation Delay 10 45 ns
t
RSSS
RESETSEL Valid to RESET HIGH 0 ns
t
RSSH
RESET HIGH to RESETSEL Not Valid 100 ns
t
RSTL
RESET LOW Time 10 ns
t
RSTH
RESET HIGH Time 10 ns
t
LDDD
LOAD LOW to LDAC Rising Time 40 ns
t
S
Settling Time 11 (dual) /10(single) µs
TABLE III. Timing Specifications (T
A
= –40°C to +85°C).
FIGURE 12. Digital Input and Output Timing.
A1
(LSB)
SDI
CLK
CS
LOAD
A0 D3
D2
D1 D0
SDI
CLK
LDAC
RESET
V
OUT
t
css
t
LD1
t
CL
t
SDO
t
CH
t
DS
t
DH
t
LD2
t
LDRW
t
S
t
RSTH
t
RSTL
t
RSSS
t
RSSH
SDO
t
CSH
t
S
±0.003%
ERROR BAND
±0.003%
ERROR BAND
RESETSEL
D15
D14
D13XXXXX
QUICK
LOAD
(MSB)
t
LDDD
LDAC
t
LDDH
t
LDDL