Datasheet
DAC7734
16
SBAS138A
www.ti.com
THEORY OF OPERATION
The DAC7734 is a quad voltage output, 16-bit Digital-to-
Analog Converter (DAC). The architecture is an R-2R
ladder configuration with the three MSBs segmented, fol-
lowed by an operational amplifier that serves as a buffer.
Each DAC has its own R-2R ladder network, segmented
MSBs, and output op amp, as shown in Figure 1. The
minimum voltage output (zero-scale) and maximum voltage
output (full-scale) are set by the external voltage references
V
REF
L and V
REF
H.
The digital input is a 24-bit serial word that contains a 2-bit
address code for selecting one of four DACs, a quick load
bit, five unused bits, and the 16-bit DAC code (MSB first).
The converters can be powered from either a single +15V
supply or a dual ±15V supply and a +5V logic supply. The
device offers a reset function that immediately sets all DAC
output voltages and DAC registers to mid-scale code 8000
H
or to zero-scale, code 0000
H
. See Figures 2 and 3 for the
basic operation of the DAC7734.
FIGURE 1. DAC7734 Architecture.
FIGURE 2. Basic Single-Supply Operation of the DAC7734.
R
2R
2R2R 2R 2R 2R 2R 2R 2R
V
REF
H
V
OUT
V
OUT
Sense
V
REF
H Sense
V
REF
L
V
REF
L Sense
R
F
NC
NC
SDI
DGND
CLK
DGND
LDAC
DGND
LOAD
DGND
CS
DGND
SDO
DGND
RSTSEL
DGND
RST
DGND
NC
NC
DGND
DGND
V
DD
V
DD
V
OUT
A Sense
V
OUT
A
AGND
V
SS
V
REF
L AB Sense
V
REF
L AB
V
REF
H AB
V
REF
H AB Sense
V
OUT
B Sense
V
OUT
B
V
OUT
C Sense
V
OUT
C
V
REF
H CD Sense
V
REF
H CD
V
REF
L CD
V
REF
L CD Sense
V
OUT
D Sense
V
OUT
D
V
SS
V
SS
AGND
AGND
V
CC
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
DAC7734
Reset DAC Registers
Chips Select
Serial Data Out
Serial Data In
Clock
Load DAC Registers
Load
NC = No Connection
0V to +10V
0V to +10V
0V to +10V
0V to +10V
+10.000V
+10.000V
+15V
0.1µF
1µF
+
0.1µF
1µF
+5V
+