Datasheet

DAC7731
13
SBAS249B
www.ti.com
V
CC
REF
OUT
REF
IN
REFADJ
V
REF
R
OFFSET
AGND
RFB2
RFB1
SJ
V
OUT
V
DD
V
SS
REFEN
RSTSEL
SCLK
CS
SDO
SDI
LDAC
RST
NC
TEST
DGND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
DAC7731
V
CC
REF
OUT
REF
IN
REFADJ
V
REF
R
OFFSET
AGND
RFB2
RFB1
SJ
V
OUT
V
DD
V
SS
REFEN
RSTSEL
SCLK
CS
SDO
SDI
LDAC
RST
NC
TEST
DGND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
DAC7731
From Host
Controller
To next
DAC7731
First Device in Chain Second Device in Chain
cycle written into the chain will arrive at the last DAC7731 on
the final cycle of the data transfer. Upon completion of the
required number of data transfer cycles (one cycle per
device), each DAC voltage output is updated with a rising
edge on the LDAC inputs. Figure 7 shows the required timing
to properly update two DAC7731s in a daisy-chained con-
figuration, as shown in Figure 8.
DAC RESET
The RST and RSTSEL inputs control the reset of the analog
output. The reset command is level triggered by a low signal on
RST. Once RST is LOW, the DAC output will begin settling to
the mid-scale or min-scale code depending on the state of the
RSTSEL input. A HIGH value on RSTSEL will cause V
OUT
to
reset to the mid-scale code (8000
H
) and a LOW value will reset
V
OUT
to min-scale (8000
H
). A change in the state of the RSTSEL
input while RST is LOW will cause a corresponding change in
the reset command selected internally and consequently change
the output value of V
OUT
of the DAC. Note that a valid reset
signal also resets the input register of the DAC to the value
specified by the state of RSTSEL.
SCLK
CS
LDAC
SDI A15 A14 A0
XX X
SDO
12 1216 16
LSBs latched LSBs latched
Both DAC V
OUT
's
are updated
First Data Transfer Cycle
Previous cycle word from host
(to DAC7731 B SDI)
B15 B14 B1 B0
A15 A14 A1 A0
FIGURE 7. DAC7731 Daisy-Chain Timing for Figure 7.
DAC via SDI and out of the DAC on SDO. Care must be taken
that the LDAC signal to the DAC(s) is timed correctly so that
valid data is transferred into the DAC register on each rising
LDAC edge. (
Valid data refers to the serial data latched on
each of the 16 rising SCLK edges prior to the occurrence of a
rising LDAC signal.) The rising edge of LDAC must occur
before the first rising SCLK edge of the following 16-bit
transfer. Figure 6 shows continuous transfer timing.
DAISY-CHAINING USING SDO
Multiple DAC7731s can be connected to a single serial port
by attaching each of their control inputs in parallel and daisy-
chaining the SDO and SDI I/Os of each device. The SDO
output of the DAC7731 is active when CS is LOW and can
be left unconnected when not required for use in a daisy-
chain configuration.
Once a data transfer cycle begins, new data is shifted into
SDI and data currently residing in the shift register (from
previous cycle, power-up, or reset command) is presented
on SDO, MSB first. One data transfer cycle for each DAC7731
is required to update all devices in the chain. The first data
FIGURE 8. DAC7731 Daisy-Chain Schematic.