Datasheet

DAC7731
4
SBAS249B
www.ti.com
PARAMETER DESCRIPTION MIN TYP MAX UNITS
t
WH
SCLK HIGH Time 25 ns
t
WL
SCLK LOW Time 25 ns
t
SDI
Setup Time: Data in valid before rising SCLK 5 ns
t
HDI
Hold Time: Data in valid after rising SCLK 20 ns
t
SCS
Setup Time: CS falling edge before first rising SCLK 15 ns
t
HSC
Hold Time: CS rising edge after 16th rising SCLK 0 ns
t
DDO
Delay Time: CS Falling Edge to Data Out valid, C
L
= 20pF on SDO 50 ns
t
HDO
Hold Time: Data Out valid after SCLK rising edge, C
L
20pF on SDO 50 ns
t
DDOZ
Delay Time: CS rising edge to SDO = High Impedance 70 ns
t
WCSH
CS HIGH Time 50 ns
t
WLDL
LDAC LOW Time 20 ns
t
WLDH
LDAC HIGH Time 20 ns
t
SLD
Setup Time: 16th Rising SCLK Before LDAC Rising Edge 15 ns
t
DLD
Delay Time: LDAC rising edge to first SCLK rising edge of next 15 ns
transfer cycle.
t
SCLK
Setup Time: CS High before falling SCLK edge following 16th 5 ns
rising SCLK edge
t
SRS
Setup Time: RSTSEL Valid Before RST LOW 0 ns
t
HRS
Hold Time: RSTSEL valid after RST HIGH 20 ns
t
WRL
RST LOW Time 30 ns
t
S
DAC V
OUT
Settling Time 5 µs
TIMING CHARACTERISTICS
V
CC
= +15V, V
SS
= –15V, V
DD
= 5V; R
L
= 2kΩ to AGND; C
L
= 200pF to AGND; all specifications –40°C to +85°C, unless otherwise noted.
DAC7731
CS
SCLK
SDI
SDO
LDAC
V
OUT
t
SCS
t
HCS
t
WH
t
WL
t
SCLK
t
HDI
t
SDI
t
DDO
t
HDO
t
DDOZ
t
WLDL
t
DLD
t
SLD
t
S
t
WLDH
t
WCSH
12 16
B15 B14 B13 B0
A15 A14 A13 A0
C15 C14 C13 C12
B15 B14 B13 B12
Word B
Word A
Word C
Word B
±0.003% of FSR
Error Bands
RSTSEL
(RSTSEL = LOW)
(RSTSEL = HIGH)
RST
V
OUT
V
OUT
t
SRS
t
HRS
t
WRL
t
S
+FS
+FS
–FS
–FS
Min-Scale
Mid-Scale
INTERFACE TIMING
RESET TIMING