Datasheet

DAC7731
12
SBAS249B
www.ti.com
The DAC code is provided via a 16-bit serial interface, as shown
in Table II. The digital input word makes up the digital code to
be loaded into the data input register of the device. A typical
data transfer and DAC output update take place as follows:
Once CS is active (LOW), the DAC7731 is enabled on the serial
bus and the 16-bit serial data transfer can begin. The serial data
is shifted into the device on each rising SCLK edge until all 16
bits are transferred (1 bit per 1 rising SCLK edge). Once
received, the data in the input register is loaded into the DAC
register upon reception of a rising edge on the LDAC input (load
command). This action updates the analog output, V
OUT
, to the
desired voltage specified by the digital input word. A rising edge
on LDAC is completely asynchronous to the serial interface of
the device and can occur at any time. Care must be taken to
ensure that the entire 16 bits of data are loaded into the input
register before issuing a LDAC active edge. Additional load
commands will have no effect on the DAC output if the data in
the input register is unchanged between rising LDAC edges.
When CS is returned HIGH, the rising edge on CS must
occur when SCLK is HIGH. Application of a rising CS edge
when SCLK is LOW will cause one additional shift in the
serial input shift register, corrupting the desired input data.
TIMING CONSIDERATIONS
The flexible interface of the DAC7731 can operate under a
number of different scenarios as is required by a host
controller. Critical timing for a 16-bit data transfer cycle is
shown in the Interface Timing section of the Timing Charac-
teristics. While this is the most common method of writing to
the DAC7731, the device accepts two additional modes of
data transfer from the host. These are byte transfer mode
and continuous transfer mode.
Byte transfer mode is especially useful when an 8-bit host is
communicating with the DAC. Data transfer can occur with-
out requiring an additional general purpose I/O pin to control
the CS input of the DAC in cycles of 16 clocks. A HIGH state
on CS stops data from coming into and out of the internal
shift register. This provides byte-wide support for 8-bit host
processors. Figure 5 is an example of the timing cycle of
such a data transfer.
The remaining data transfer mode accepted by the DAC7731
is continuous transfer. The CS of the DAC7731 can be tied
LOW or held LOW by the controller for an indefinite number of
serial clock cycles. Each clock cycle will transfer data into the
16-Bit Data Word
Most Significant Byte Least Significant Byte
Byte 1, Word N
Byte 2, Word N
Byte 1, Word N – 1
Byte 2, Word N – 1
B15
A15 A14 A13 A8
A7
A6
A0
B14 B13 B8 B7 B6 B0
12 8 910
16
CS
SCLK
SDI
SDO
LDAC
1 2 16 1 2 16 1 2
B15 B14 B1 B0 C15 C14 C1 C0 D15 D14
C14C15B0B1B14B15A0A1A14A15
Word N Word N + 1 Word N + 2
Word N – 1 Word N Word N + 1
CS
SCLK
SDI
SDO
LDAC
FIGURE 6. Continuous Transfer Control.
FIGURE 5. Byte-Wide Data Write Cycle.