Datasheet

15
®
DAC7724, 7725
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
RCS
CS LOW for Read 200 ns
t
RDS
R/W HIGH to CS LOW 10 ns
t
RDH
R/W HIGH after CS HIGH 10 ns
t
DZ
CS HIGH to Data Bus in High Impedance 100 ns
t
CSD
CS LOW to Data Bus Valid 100 160 ns
t
WCS
CS LOW for Write 50 ns
t
WS
R/W LOW to CS LOW 0 ns
t
WH
R/W LOW after CS HIGH 0 ns
t
AS
Address Valid to CS LOW 0 ns
t
AH
Address Valid after CS HIGH 0 ns
t
LD
LDAC Delay from CS HIGH 10 ns
t
DS
Data Valid to CS LOW 0 ns
t
DH
Data Valid after CS HIGH 0 ns
t
LWD
LDAC LOW 50 ns
t
RESET
RESET LOW Time 50 ns
t
S
Settling Time 10 µs
TABLE II. Timing Specifications (T
A
= –40°C to +85°C).
FIGURE 4. Digital Input and Output Timing.
t
RCS
CS
t
RDS
t
RDH
t
AS
t
CSD
t
DZ
t
AH
R/W
A0/A1
Data Out
Data Valid
Data Read Timing
±0.012% of FSR
Error Band
±0.012% of FSR
Error Band
Mid-Scale
RESET
V
OUT
, DAC7725
+FS
–FS
V
OUT
, DAC7724
+FS
–FS
DAC7724/25 Reset Timing
t
RESET
t
S
t
WCS
CS
t
WS
t
AS
t
AH
t
WH
R/W
A0/A1
t
S
±0.012% of FSR
Error Band
±0.012% of FSR
Error Band
LDAC
t
DS
t
DH
Data In
V
OUT
Data Write Timing
t
LWD
t
LD