Datasheet

5
®
DAC7715
PIN CONFIGURATION—U Package
Top View SOIC
PIN DESCRIPTIONS—U Package
PIN LABEL DESCRIPTION
1V
CC
Positive Supply Voltage, +15V nominal.
2V
OUTD
DAC D Voltage Output
3V
OUTC
DAC C Voltage Output
4V
REFL
Reference Input Voltage Low. Sets minimum out-
put voltage for all DACs.
5V
REFH
Reference Input Voltage High. Sets maximum out-
put voltage for all DACs.
6V
OUTB
DAC B Voltage Output
7V
OUTA
DAC A Voltage Output
8V
SS
Negative Supply Voltage, 0V or –15V nominal.
9 GND Ground
10 SDI Serial Data Input
11 CLK Serial Data Clock
12 CS Chip Select Input
13 LOADDACS All DAC registers become transparent when
LOADDACS is LOW. They are in the latched state
when LOADDACS is HIGH.
14 LOADREG The selected input register becomes transparent
when LOADREG is LOW. It is in the latched state
when LOADREG is HIGH.
15 RESET Asynchronous Reset Input. Sets DAC and input
registers to either zero-scale (000
H
) or mid-scale
(800
H
) when LOW. RESETSEL determines which
code is active.
16 RESETSEL When LOW, a LOW on RESET will cause the DAC
and input registers to be set to code 000
H
. When
RESETSEL is HIGH, a LOW on RESET will set the
registers to code 800
H
.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
V
OUTD
V
OUTC
V
REFL
V
REFH
V
OUTB
V
OUTA
V
SS
RESETSEL
RESET
LOADREG
LOADDACS
CS
CLK
SDI
GND
DAC7715U