Datasheet

15
®
DAC7714
Digital Input Coding
The DAC7714 input data is in Straight Binary format. The
output voltage is given by the following equation:
V V
V V N
OUT REFL
REFH REFL
= +
•( – )
4096
where N is the digital input code (in decimal). This equation
does not include the effects of offset (zero-scale) or gain
(full-scale) errors.
LAYOUT
A precision analog component requires careful layout, ad-
equate bypassing, and clean, well-regulated power supplies.
As the DAC7714 offers single-supply operation, it will often
be used in close proximity with digital logic, microcontrollers,
microprocessors, and digital signal processors. The more
digital logic present in the design and the higher the switch-
ing speed, the more difficult it will be to achieve good
performance from the converter.
Because the DAC7714 has a single ground pin, all return
currents, including digital and analog return currents, must
flow through the GND pin. Ideally, GND would be con-
nected directly to an analog ground plane. This plane would
be separate from the ground connection for the digital
components until they were connected at the power entry
point of the system.
The power applied to V
CC
(as well as V
SS
, if not grounded)
should be well regulated and low noise. Switching power
supplies and DC/DC converters will often have high-fre-
quency glitches or spikes riding on the output voltage. In
addition, digital components can create similar high-fre-
quency spikes as their internal logic switches states. This
noise can easily couple into the DAC output voltage through
various paths between the power connections and analog
output.
CS
(1)
CLK
(1)
LOADDACS RESET SERIAL SHIFT REGISTER
H
(2)
X
(3)
H H No Change
L
(4)
L H H No Change
L ↑
(5)
H H Advanced One Bit
↑ L H H Advanced One Bit
H
(6)
XL
(7)
H No Change
H
(6)
XHL
(8)
No Change
NOTES: (1) CS and CLK are interchangeable. (2) H = Logic HIGH. (3) X =
Don’t Care. (4) L = Logic LOW (5) = Positive Logic Transition. (6) A HIGH
value is suggested in order to avoid a “false clock” from advancing the shift
register and changing the shift register. (7) If data is clocked into the serial
register while LOADDACS is LOW, the selected DAC register will change as
the shift register bits “flow” through A1 and A0. This will corrupt the data in
each DAC register that has been erroneously selected. (8) RESET LOW
causes no change in the contents of the serial shift register.
TABLE III. Serial Shift Register Truth Table.