Datasheet

OUT
V ( )
SR max
t
t
æ ö
D
=
ç ÷
D
è ø
DAC7678
SBAS493B –FEBRUARY 2010–REVISED JULY 2012 www.ti.com
Power-Supply Rejection Ratio (PSRR) Channel-to-Channel DC Crosstalk
Power-supply rejection ratio (PSRR) is defined as the Channel-to-channel dc crosstalk is defined as the dc
ratio of change in output voltage to a change in change in the output level of one DAC channel in
supply voltage for a full-scale output of the DAC. The response to a change in the output of another DAC
PSRR of a device indicates how the output of the channel. It is measured with a full-scale output
DAC is affected by changes in the supply voltage. change on one DAC channel while monitoring
PSRR is measured in decibels (dB). another DAC channel remains at midscale. It is
expressed in LSB.
Monotonicity
DAC Output Noise Density
Monotonicity is defined as a slope whose sign does
not change. If a DAC is monotonic, the output Output noise density is defined as internally-
changes in the same direction or remains at least generated random noise. Random noise is
constant for each step increase (or decrease) in the characterized as a spectral density (nV/√Hz). It is
input code. measured by loading the DAC to midscale and
measuring noise at the output.
DYNAMIC PERFORMANCE
DAC Output Noise
Dynamic performance parameters are specifications
DAC output noise is defined as any voltage deviation
such as settling time or slew rate, which are important
of DAC output from the desired value (within a
in applications where the signal rapidly changes
particular frequency band). It is measured with a DAC
and/or high frequency signals are present.
channel kept at midscale while filtering the output
voltage within a band of 0.1Hz to 10Hz and
Slew Rate
measuring its amplitude peaks. It is expressed in
The output slew rate (SR) of an amplifier or other
terms of peak-to-peak voltage (Vpp).
electronic circuit is defined as the maximum rate of
Full-Scale Range (FSR)
change of the output voltage for all possible input
signals.
Full-scale range (FSR) is the difference between the
maximum and minimum analog output values that the
DAC is specified to provide; typically, the maximum
and minimum values are also specified. For an n-bit
DAC, these values are usually given as the values
Where ΔV
OUT
(t) is the output produced by the
matching with code 0 and 2
n
–1.
amplifier as a function of time t.
LAYOUT
Output Voltage Settling Time
Settling time is the total time (including slew time) for
A precision analog component requires careful layout,
the DAC output to settle within an error band around
adequate bypassing, and clean, well-regulated power
its final value after a change in input. Settling times
supplies. The DAC7678 offers single-supply
are specified to within ±0.003% (or whatever value is
operation, and is often used in close proximity with
specified) of full-scale range (FSR).
digital logic, microcontrollers, microprocessors, and
digital signal processors. The more digital logic
Code Change/Digital-to-Analog Glitch Energy
present in the design and the higher the switching
Digital-to-analog glitch impulse is the impulse injected
speed, the more difficult it is to keep digital noise
into the analog output when the input code in the
from appearing at the output. As a result of the single
DAC register changes state. It is normally specified
ground pin of the DAC7678, all return
as the area of the glitch in nanovolt-seconds (nV-s),
currents(including digital and analog return currents
and is measured when the digital input code is
for the DAC) must flow through a single point. Ideally,
changed by 1LSB at the major carry transition.
GND would be connected directly to an analog
Digital Feed-through
ground plane. This plane would be separate from the
ground connection for the digital components until
Digital feed-through is defined as impulse seen at the
they were connected at the power-entry point of the
output of the DAC from the digital inputs of the DAC.
system.
It is measured when the DAC output is not updated. It
is specified in nV-s, and measured with a full-scale
The power applied to AVDD should be well-regulated
code change on the data bus; that is, from all '0's to
and low noise. Switching power supplies and dc/dc
all '1's and vice versa.
converters often have high-frequency glitches or
spikes riding on the output voltage. In addition, digital
components can create similar high-frequency spikes
as their internal logic switches states. This noise can
easily couple into the DAC output voltage through
various paths between the power connections and
42 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): DAC7678