Datasheet

Amplifier
Resistor
String
DAC
Power-Down
Circuitry
Resistor
Network
V X
OUT
DAC7678
SBAS493B –FEBRUARY 2010–REVISED JULY 2012 www.ti.com
When both the PD0 and PD1 bits are set to '0', the SPACER
device works normally with its typical consumption of
1.49 mA at 5.5V. The reference is included with the
CLEAR CODE REGISTER AND CLR PIN
operation of all eight channels. However, for the three
The DAC7678 contains a clear code register. The
power-down modes, the supply current falls to 0.42
clear code register can be accessed via the serial
µA at 5.5V (0.25 µA at 2.7V). Not only does the
interface (I
2
C) and is user configurable. Bringing the
supply current fall, but the output stage also switches
CLR pin low clears the contents of all DAC registers
internally from the output amplifier to a resistor
and all DAC buffers and replaces the code with the
network of known values as shown in Figure 93.
code determined by the clear code register. The clear
The advantage of this switching is that the output
code register can be written to by applying the
impedance of the device is known while it is in power-
commands shown in Table 17. The default setting of
down mode. As described in Table 19, there are
the clear code register sets the output of all DAC
three different power-down options. V
OUT
can be
channels to 0V when the CLR pin is brought low. The
connected internally to GND through a 1kΩ resistor, a
CLR pin is falling-edge triggered; therefore, the
100kΩ resistor, or open-circuited (High-Z). In other
device exits clear code mode on the falling edge of
words, C3, C2, C1, and C0 = '0100' and DB14 and
the acknowledge signal that follows LSDB of the next
DB13 = '11' represent a power-down condition with
write sequence. If the CLR pin is executed (brought
High-Z output impedance for a selected channel.
low) during a write sequence, this write sequence is
DB14 and DB13 = '01' represents a power-down
aborted and the DAC registers and DAC buffers are
condition with 1kΩ output impedance and '10'
cleared as described above.
represents a power-down condition with 100kΩ
When performing a software reset of the device, the
output impedance.
clear code register is reset to the default mode (DB5
= '0', DB4 = '0'). Setting the clear code register to
Table 19. DAC Operating Modes
DB4 = '1' and DB5 = '1' ignores any activity on the
PD1 PD0
external CLR pin.
DAC OPERATING MODES
(DB14) (DB13)
0 0 Power on selected DACs
SOFTWARE RESET FUNCTION
0 1 Power down selected DACs, 1kΩ to GND
The DAC7678 contains a software reset feature.
1 0 Power down selected DACs, 100kΩ to GND
When the software reset feature is executed, the
1 1 Power down selected DACs, High-Z to GND
device (all DAC channels) are reset to the power-on
reset code. All registers inside the device are reset to
SPACER
the respective default settings. The DAC7678 has an
additional feature of switching straight to high speed
mode after reset. Table 20 shows all the different
modes of the software reset function.
Table 20. Software Reset Modes
DB15 DB14 OPERATING MODES
Default Software reset. Equivalent to Power-
0 0
on-Reset
Software reset and set part in High Speed
x 1
Mode
Software reset and maintain High Speed
1 0
Mode state
Figure 93. Output Stage During Power-Down
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