Datasheet

DAC7678
SBAS493B –FEBRUARY 2010–REVISED JULY 2012 www.ti.com
Table 17. Control Matrix for Write Commands (continued)
COMMAND AND ACCESS BYTE MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE
DESCRIPTION
C3 C2 C1 C0 A3 A2 A1 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Write to Select DAC Input Register and Update All DAC Registers (Global Software LDAC)
Write to DAC input register of channel A and
0 0 1 0 0 0 0 0 Data[11:4] Data[3:0] X X X X
update all DAC registers
Write to DAC input register of channel B and
0 0 1 0 0 0 0 1 Data[11:4] Data[3:0] X X X X
update all DAC registers
Write to DAC input register of channel C and
0 0 1 0 0 0 1 0 Data[11:4] Data[3:0] X X X X
update all DAC registers
Write to DAC input register of channel D and
0 0 1 0 0 0 1 1 Data[11:4] Data[3:0] X X X X
update all DAC registers
Write to DAC input register of channel E and
0 0 1 0 0 1 0 0 Data[11:4] Data[3:0] X X X X
update all DAC registers
Write to DAC input register of channel F and
0 0 1 0 0 1 0 1 Data[11:4] Data[3:0] X X X X
update all DAC registers
Write to DAC input register of channel G and
0 0 1 0 0 1 1 0 Data[11:4] Data[3:0] X X X X
update all DAC registers
Write to DAC input register of channel H and
0 0 1 0 0 1 1 1 Data[11:4] Data[3:0] X X X X
update all DAC registers
0 0 1 0 1 X X X X X X X X X X X X X X X X X X X Invalid code, no action performed
Broadcast mode–write to all input registers and
0 0 1 0 1 1 1 1 Data[11:4] Data[3:0] X X X X
update all DAC registers
Power-Down Register
0 1 0 0 X X X X X PD1 PD0 DAC H DAC G DAC F DAC E DAC D DAC C DAC B DAC A X X X X X
0 1 0 0 X X X X X 0 0 DAC H DAC G DAC F DAC E DAC D DAC C DAC B DAC A X X X X X Each DAC bit set to '1' powers on selected DACs
Each DAC bit set to '1' powers down selected
0 1 0 0 X X X X X 0 1 DAC H DAC G DAC F DAC E DAC D DAC C DAC B DAC A X X X X X DACs. V
OUT
connected to GND through 1kΩ pull-
down resistor
Each DAC bit set to '1' powers down selected
0 1 0 0 X X X X X 1 0 DAC H DAC G DAC F DAC E DAC D DAC C DAC B DAC A X X X X X DACs. V
OUT
connected to GND through 100kΩ
pull-down resistor
Each DAC bit set to '1' powers down selected
0 1 0 0 X X X X X 1 1 DAC H DAC G DAC F DAC E DAC D DAC C DAC B DAC A X X X X X
DACs. V
OUT
is High Z
Clear Code Register
0 1 0 1 X X X X X X X X X X X X X X CL1 CL0 X X X X
Write to clear code register, CLR pin will clear to
0 1 0 1 X X X X X X X X X X X X X X 0 0 X X X X
zero scale
Write to clear code register, CLR pin will clear to
0 1 0 1 X X X X X X X X X X X X X X 0 1 X X X X
midscale
Write to clear code register, CLR pin will clear to
0 1 0 1 X X X X X X X X X X X X X X 1 0 X X X X
full scale
0 1 0 1 X X X X X X X X X X X X X X 1 1 X X X X Write to clear code register disables CLR pin
LDAC Register
When all DAC bits are set to '1', selected DACs
ignore the LDAC pin.
0 1 1 0 X X X X DAC H DAC G DAC F DAC E DAC D DAC C DAC B DAC A X X X X X X X X
When all DAC bits are set to '0', selected DAC
registers update according to the LDAC pin.
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