Datasheet

DAC7678
SBAS493B –FEBRUARY 2010–REVISED JULY 2012 www.ti.com
Table 7. Update Sequence
MSB ··· LSB MSB ··· LSB MSB ··· LSB MSB ··· LSB
ACK ACK ACK ACK
Address (A) Byte Command/Access Byte MSDB LSDB
DB[32:24] DB[23:16] DB[15:8] DB[7:0]
SPACING
The CA byte sets the operational mode of the maximum DAC update rate is limited to 22.22kSPS.
selected DAC7678. When the operational mode is Using the Fast mode plus (clock = 1MHz), the
selected by this byte, the DAC7678 must receive two maximum DAC update rate is limited to 55.55kSPS.
data bytes, the most significant data byte (MSDB) When a stop condition is received, the DAC7678
and least significant data byte (LSDB), for data releases the I
2
C bus and awaits a new start condition.
update to occur. The DAC7678 performs an update
on the falling edge of the acknowledge signal that Address (A) Byte
follows the LSDB.
The address byte, as shown in Table 8, is the first
The CA byte does not have to be resent until a byte received following the START condition from the
change in operational mode is required. The bits of master device. The first four bits (MSBs) of the
the control byte continuously determine the type of address are factory preset to 1001. The next 3 bits of
update performed. Thus, for the first update, the the address are controlled by the ADDR pin(s). The
DAC7678 requires a start condition, a valid I
2
C ADDR pin(s) inputs can be connected to AV
DD
, GND,
address, the CA byte, and two data bytes (MSDB and or left floating. The device address should be
LSDB). For all consecutive updates, the DAC7678 determined before device power up. During power up
needs only an MSDB and LSDB, as long as the CA the device latches the values of the address pins and
byte command remains the same. consequently will respond to that particular address
according to Table 9 and Table 10. When using the
When using the I
2
C HS mode (clock = 3.4MHz), each
QFN package (DAC7678RGE), up to 8 devices can
12-bit DAC update other than the first update can be
be connected to the same I
2
C bus. When using the
done within 18 clock cycles (MSDB, acknowledge
TSSOP package (DAC7678PW), up to 3 devices can
signal, LSDB, acknowledge signal) at 188.88kSPS.
be connected to the same I
2
C bus.
When using Fast mode (clock = 400kHz), the
Table 8. Address Byte
MSB LSB
AD6 AD5 AD4 AD3 AD2 AD1 AD0 R/W
1 0 0 1 See Table 9 or Table 10 Slave Address column 0 or 1
Table 9. Address Format For QFN-24 (RGE) Package
SLAVE ADDRESS ADDR1 ADDR0
1001 000 0 0
1001 001 0 1
1001 010 1 0
1001 011 1 1
1001 100 Float 0
1001 101 Float 1
1001 110 0 Float
1001 111 1 Float
Not supported Float Float
Table 10. Address Format For TSSOP-16 (PW) Package
SLAVE ADDRESS ADDR0
1001 000 0
1001 010 1
1001 100 Float
28 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): DAC7678