Datasheet

Generate ACKNOWLEDGE
Signal
Acknowledgement
Signal From Slave
SDA
SCL
MSB
P
Sr
Sr
or
P
S
or
Sr
START or
REPEATED START
Condition
Clock Line Held Low While
Interrupts are Serviced
1 2 7 8 9
ACK
1 2 3 - 8 9
ACK
Address
R/W
Recognize START or
REPEATED START
Condition
REPEATED START
STOP
or
Condition
Recognize STOP or
REPEATED START
Condition
ChangeofDataAllowed
DataLineStable;
DataValid
SDA
SCL
DAC7678
www.ti.com SBAS493B –FEBRUARY 2010–REVISED JULY 2012
necessary. all devices must recognize it and switch their
internal setting to support 3.4Mbps operation.
• To signal the end of the data transfer, the master
generates a stop condition by pulling the SDA line • The master then generates a repeated start
from low to high while the SCL line is high (see condition (a repeated start condition has the same
Figure 89). This action releases the bus and stops timing as the start condition). After this repeated
the communication link with the addressed slave. start condition, the protocol is the same as F/S-
All I
2
C-compatible devices recognize the stop mode, except that transmission speeds up to
condition. Upon receipt of a stop condition, the 3.4Mbps are allowed. A stop condition ends HS
bus is released, and all slave devices then wait for mode and switches all the internal settings of the
a start condition followed by a matching address. slave devices to support F/S-mode. Instead of
using a stop condition, repeated start conditions
should be used to secure the bus in H/S-mode.
DAC7678 I
2
C UPDATE SEQUENCE
For a single update, the DAC7678 requires a start
condition, a valid I
2
C address, a command and
access (CA) byte, and two data bytes, the most
significant data byte (MSDB) and least significant
Figure 91. Bit Transfer on the I
2
C Bus
data byte (LSDB), as shown in Table 7.
After each byte is received, the DAC7678
HS Mode Protocol
acknowledges by pulling the SDA line low during the
high period of a single clock pulse, as shown in
• When the bus is idle, both the SDA and SCL lines
Figure 92. These four bytes and acknowledge cycles
are pulled high by the pull-up resistors.
make up the 36 clock cycles required for a single
• The master generates a start condition followed
update to occur. A valid I
2
C address selects the
by a valid serial byte containing H/S master code
DAC7678.
00001XXX. This transmission is made in F/S
mode at no more than 1.0 Mbps. No device is
allowed to acknowledge the H/S master code, but
Figure 92. I
2
C Bus Protocol
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