Datasheet

Start
Condition
SDA
Stop
Condition
SDA
SCL
S P
SCL
NotAcknowledge
Acknowledge
1 2 8 9
ClockPulsefor
Acknowledgement
S
START
Condition
DataOutput
byTransmitter
DataOutput
byReceiver
SCLfrom
Master
DAC7678
SBAS493B –FEBRUARY 2010–REVISED JULY 2012 www.ti.com
TWO-WIRE, I
2
C-COMPATIBLE INTERFACE and fast modes. The protocol for high-speed mode is
different from the F/S-mode, and it is referred to as
The I
2
C™ is a 2-wire serial interface developed by
HS-mode. The DAC7678 supports 7-bit addressing.
Philips Semiconductor (see I
2
C™-Bus Specification,
The 10-bit addressing and general call address are
Rev. 03, June 2007). The bus consists of a data line
not supported.
(SDA) and a clock line (SCL) with pull-up structures.
When the bus is idle, both SDA and SCL lines are Other than specific timing signals, the I
2
C interface
pulled high. All the I
2
C™ compatible devices connect works with serial bytes. At the end of each byte, a 9
th
to the I
2
C™ bus through open drain I/O pins, SDA clock cycle is used to generate/detect an
and SCL. acknowledge signal, Acknowledge is when the SDA
line is pulled low during the high period of the 9
th
The I
2
C specification states that the device that
clock cycle. A not-acknowledge is when the SDA line
controls communication is called a master, and the
is left high during the high period of the 9
th
clock
devices that are controlled by the master are called
cycle as shown in Figure 90.
slaves. The master device generates the SCL signal.
The master device also generates special timing
conditions (start condition, repeated start condition,
and stop condition) on the bus to indicate the start or
stop of a data transfer. Device addressing is also
done by the master. The master device on an I
2
C bus
is usually a microcontroller or a digital signal
processor (DSP). The DAC7678 on the other hand,
operates as a slave device on the I
2
C bus. A slave
devcie acknowledges master's commands and upon
master's control, either receives or transmits data.
Figure 90. Acknowledge and Not Acknowledge
on the I
2
C Bus
F/S Mode Protocol
• The master initiates data transfer by generating a
start condition. The start condition is when a high-
to-low transition occcurs on the SDA line while
SCL is high, as shown in Figure 90. All I
2
C-
Figure 89. Start and Stop Conditions
compatible devices recognize a start condition.
• The master then generates the SCL pulses, and
The DAC7678 normally operates as a slave receiver.
transmits the 7-bit address and the read/write
A master device writes to the DAC7678, a slave
direction bit (R/W) on the SDA line. During all
receiver. However, if a master device inquires the
transmissions, the master ensures that data is
DAC7678 internal register data, the DAC7678
valid. A valid data condition requires the SDA line
operates as a slave transmitter. In this case, the
to be stable during the entire high period of the
master device reads from the DAC7678, a slave
clock pulse, as shown in Figure 91. All devices
transmitter. According to I
2
C™ terminology, read and
recognize the address sent by the master and
write are with respect to the master device.
compare it to their internal fixed addresses. Only
The DAC7678 works as a slave and supports the
the slave device with a matching address
following data transfer modes, as defined in the I
2
C™
generates an acknowledge by pulling the SDA line
-Bus Specification:
low during the entire high period of the ninth SCL
• Standard mode (100 kbps)
cycle, as shown in Figure 90 by pulling the SDA
line low during the entire high period of the 9
th
• Fast mode (400 kbps)
SCL cycle. Upon detecting this acknowledge, the
• Fast mode+ (1.0Mbps) and
master knows the communication link with a slave
• High-Speed mode (3.4 Mbps)
has been established.
The data transfer protocol for standard and fast
• The master generates further SCL cycles to either
modes is exactly the same, therefore they are
transmit data to the slave (R/W bit 0) or receive
referred to as F/S-mode in this document. The fast
data from the slave (R/W bit 1). In either case, the
mode+ protocol is supported in terms of data transfer
receiver needs to acknowledge the data sent by
speed but not output current. The low-level output
the transmitter. So the acknowledge signal can
current would be 3mA similar to the case of standard
either be generated by the master or by the slave,
depending on which one is the receiver. The 9-bit
valid data sequences, consisting of 8-data bits
and 1-bit acknowledge can continue as long as
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