Datasheet

20
®
DAC7644
DIGITAL TIMING
Figure 14 and Table II provide detailed timing for the digital
interface of the DAC7644.
DIGITAL INPUT CODING
The DAC7644 input data is in Straight Binary format. The
output voltage is given by Equation 1.
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
RCS
CS LOW for Read 150 ns
t
RDS
R/W HIGH to CS LOW 10 ns
t
RDH
R/W HIGH after CS HIGH 10 ns
t
DZ
CS HIGH to Data Bus in High Impedance 10 100 ns
t
CSD
CS LOW to Data Bus Valid 100 150 ns
t
WCS
CS LOW for Write 40 ns
t
WS
R/W LOW to CS LOW 0 ns
t
WH
R/W LOW after CS HIGH 10 ns
t
AS
Address Valid to CS LOW 0 ns
t
AH
Address Valid after CS HIGH 10 ns
t
LS
CS LOW to LOADDACS HIGH 30 ns
t
LH
CS LOW after LOADDACS HIGH 100 ns
t
LX
LOADDACS HIGH 100 ns
t
DS
Data Valid to CS LOW 0 ns
t
DH
Data Valid after CS HIGH 10 ns
t
LWD
LOADDACS LOW 100 ns
t
SS
RSTSEL Valid Before RESET HIGH 0 ns
t
SH
RSTSEL Valid After RESET HIGH 200 ns
t
RSS
RESET LOW Before RESET HIGH 10 ns
t
RSH
RESET LOW After RESET HIGH 10 ns
t
S
Settling Time 10 µs
TABLE II. Timing Specifications (T
A
= –40°C to +85°C).
t
RCS
CS
t
RDS
t
RDH
t
AS
t
CSD
t
DZ
t
AH
R/W
A0/A1
Data Out
Data Valid
t
WCS
CS
t
WS
t
AS
t
AH
t
WH
R/W
A0/A1
t
LS
t
LWD
t
LH
t
S
±0.003% of FSR
Error Band
±0.003% of FSR
Error Band
t
LX
LOADDACS
t
DS
t
DH
Data In
V
OUT
Data Read Timing
Data Write Timing
t
RSH
RST
V
OUT
,RESET SEL LOW
+FS
–FS
t
SS
t
SH
RESET SEL
V
OUT
,RESET SEL HIGH
MS
+FS
–FS
DAC7644 Reset Timing
t
RSS
where N is the digital input code. This equation does not
include the effects of offset (zero-scale) or gain (full-scale)
errors.
FIGURE 14. Digital Input and Output Timing.
(1)
VVL
VHVLN
OUT REF
REF REF
=+
()
–•
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