Datasheet

19
®
DAC7644
3.0
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +25°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
FIGURE 11. Linearity and Differential Linearity Error Curves
for Figure 10.
NC
NC
NC
NC
V
OUT
A Sense
V
OUT
A
V
REF
L AB Sense
V
REF
L AB
V
REF
H AB
V
REF
H AB Sense
V
OUT
B Sense
V
OUT
B
48
47
46
45
44
43
42
41
40
39
38
37
DAC7644
+2.5V
+V
V
OUT
V
OUT
FIGURE 12. Low Cost Single-Supply Configuration.
FIGURE 13. Linearity and Differential Linearity Error Curves
for Figure 12.
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +25°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
DIGITAL INTERFACE
Table I shows the basic control logic for the DAC7644. Note
that each internal register is edge triggered and not level
triggered. When the LOADDACS signal is transitioned to
HIGH, the digital word currently in the register is latched.
The first set of registers (the input registers) are triggered via
the A0, A1, R/W, and CS inputs. Only one of these registers
is transparent at any given time.
The double-buffered architecture is designed mainly so each
DAC input register can be written to at any time and then all
DAC voltages updated simultaneously by the rising edge of
LOADDACS. It also allows a DAC input register to be
written to at any point and the DAC voltages to be synchro-
nously changed via a trigger signal connected to
LOADDACS.
INPUT DAC
A1 A0 R/W CS RST RSTSEL
LOADDACS REGISTER REGISTER MODE DAC
LLLLHXX Write Hold Write Input A
L H L L H X X Write Hold Write Input B
H L L L H X X Write Hold Write Input C
H H L L H X X Write Hold Write Input D
L L H L H X X Read Hold Read Input A
L H H L H X X Read Hold Read Input B
H L H L H X X Read Hold Read Input C
H H H L H X X Read Hold Read Input D
XXXHHX↑ Hold Write Update All
X X X H H X H Hold Hold Hold All
XXXX↑ L X Reset to Zero Reset to Zero All
XXXX↑ H X Reset to Midscale Reset to Midscale All
TABLE I. DAC7644 Logic Truth Table.