Datasheet

DAC7642, DAC7643
17
SBAS233
www.ti.com
INPUT DAC
DACSEL R/W CS RST LOADDACS REGISTER REGISTER MODE DAC
L L L L, H X Write Hold Write Input A
H L L L, H X Write Hold Write Input B
L H L L, H X Read Hold Read Input A
H H L L, H X Read Hold Read Input B
X X H L, H ↑ Hold Write Update All
X X H L, H L, H Hold Hold Hold All
XXX↑ L, H Reset Reset Reset All
TABLE I. DAC7642 and DAC7643 Logic Truth Table.
t
RCS
CS
t
RDS
t
RDH
t
AS
t
CSD
t
DZ
t
AH
R/W
DACSEL
Data Out
Data Valid
t
WCS
CS
t
WS
t
AS
t
AH
t
WH
R/W
DACSEL
t
LS
t
LWD
t
LH
t
S
±0.003% of FSR
Error Band
±0.003% of FSR
Error Band
t
LX
LOADDACS
t
DS
t
DH
Data In
V
OUT
t
S
Data Read Timing
Data Write Timing
t
RSH
RST
V
OUT
+FS
–FS
(DAC7643)
Zero-Scale
V
OUT
+FS
–FS
(DAC7642)
Midscale
t
RSS
FIGURE 14. Digital Input and Output Timing.
(1)
DIGITAL TIMING
Figure 14 and Table II provide detailed timing for the digital
interface of the DAC7642 and DAC7643.
DIGITAL INPUT CODING
The DAC7642 and DAC7643 input data is in Straight Binary
format. The output voltage is given by Equation 1:
VVL
VHVLN
OUT
REF
REF REF
=+
( )
–•
,65 536
where N is the digital input code. This equation does not
include the effects of offset (zero-scale) or gain (full-scale)
errors.