Datasheet

DAC7642, DAC7643
16
SBAS233
www.ti.com
V
OUT
A
V
OUT
A Sense
V
REF
L Sense
V
REF
L
V
REF
H
V
REF
H Sense
V
OUT
B Sense
V
OUT
B
32
31
30
29
28
27
26
25
DAC7642
DAC7643
V
OUT
V
OUT
+2.5V
+V
FIGURE 11. Linearity and Differential Linearity Error Curves
for Figure 10.
FIGURE 13. Linearity and Differential Linearity Error Curves
for Figure 12.
FIGURE 12. Low-Cost Single-Supply Configuration.
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +25°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +25°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
FIGURE 10. Single-Supply Buffered V
REF
H.
V
OUT
A
V
OUT
A Sense
V
REF
L Sense
V
REF
L
V
REF
H
V
REF
H Sense
V
OUT
B Sense
V
OUT
B
32
31
30
29
28
27
26
25
DAC7642
DAC7643
V
OUT
V
OUT
+V
OPA2350
+2.5V
+V
1000pF
100Ω
2200pF
DIGITAL INTERFACE
See Table I for the basic control logic of the DAC7642 and
DAC7643. Note that each internal register is edge triggered
and not level triggered. When the LOADDACS signal is
transitioned from LOW to HIGH, the digital word existing in
the input register is latched into the DAC register. The first
set of registers (the input registers) are triggered via the
DACSEL, R/W, and CS inputs. Only one of these registers
can be transparent at any given time.
The double-buffered architecture is designed mainly so each
DAC input register can be written to at any time without
affecting the DAC outputs. All DAC voltages are updated
simultaneously by the rising edge of LOADDACS. It also
allows multiple devices to be updated simultaneously by
sharing the LOADDACS control from the host with each
device.