Datasheet

DAC7642, DAC7643
12
SBAS233
www.ti.com
THEORY OF OPERATION
The DAC7642 and DAC7643 are dual channel, voltage
output, 16-bit DACs. The architecture is an R-2R ladder
configuration with the three MSBs segmented followed by an
operational amplifier that serves as a buffer. Each DAC has
its own R-2R ladder network, segmented MSBs, and output
op amp, as shown in Figure 1. The minimum voltage output
(zero-scale) and maximum voltage output (full-scale) are set
by the external voltage references V
REF
L and V
REF
H, respec-
tively. The digital input is a 16-bit parallel word and the DAC
input registers offer a readback capability. The converters
can be powered from either a single +5V supply or a dual
±5V supply. Each device offers a reset function which imme-
diately sets all DAC output voltages, DAC registers and Input
registers to mid-scale, code 8000
H
(DAC7642), or to zero-
scale, code 0000
H
(DAC7643). See Figures 2 and 3 for the
basic configurations of the DAC7642 and DAC7643.
FIGURE 1. DAC7642 and DAC7643 Architecture.
R
2R
2R2R 2R 2R 2R 2R 2R 2R
V
REF
H
V
OUT
V
OUT
Sense
V
REF
H Sense
V
REF
L
V
REF
L Sense
R
F
TYPICAL CHARACTERISTICS: V
SS
= 5V (Cont.)
At T
A
= +25°C, V
CC
= +5V, V
SS
= 5V, V
REF
H
= +2.5V, V
REF
L
= 2.5V, representative unit, unless otherwise specified.
Time (1µs/div)
OUTPUT VOLTAGE
vs MIDSCALE GLITCH PERFORMANCE
Output Voltage (50mV/div)
+5V
LDAC
0
7FFF
H
to 8000
H
Time (1µs/div)
OUTPUT VOLTAGE
vs MIDSCALE GLITCH PERFORMANCE
Output Voltage (50mV/div)
+5V
LDAC
0
8000
H
to 7FFF
H