Datasheet

5
®
DAC7641
19 LDAC DAC Load Strobe, rising-edge triggered.
20 RST Reset, rising-edge triggered. Depending on the state
of RSTSEL, the DAC registers are set to either mid-
scale or zero.
21 RSTSEL Reset Select. Determines the action of RST. If
HIGH, a RST command will set the DAC registers to
mid-scale. If LOW, a RST command will set the DAC
registers to zero.
22 V
OUT
DAC Voltage Output
23 V
OUT
Sense DAC Output Amplifier Inverting Input. Used to close
the feedback loop at the load.
24 V
SS
Negative Power Supply
25 AGND Analog Ground
26 V
CC
Positive Power Supply
27 V
REFH
Sense DAC Reference High Sense Input
28 V
REFH
DAC Reference High Input
29 V
REFL
Sense DAC Reference Low Sense Input
30 V
REFL
DAC Reference Low Input
31 DGND Digital Ground
32 V
DD
Positive Power Supply
PIN NAME DESCRIPTION
1 DB15 Data Bit 15, MSB
2 DB14 Data Bit 14
3 DB13 Data Bit 13
4 DB12 Data Bit 12
5 DB11 Data Bit 11
6 DB10 Data Bit 10
7 DB9 Data Bit 9
8 DB8 Data Bit 8
9 DB7 Data Bit 7
10 DB6 Data Bit 6
11 DB5 Data Bit 5
12 DB4 Data Bit 4
13 DB3 Data Bit 3
14 DB2 Data Bit 2
15 DB1 Data Bit 1
16 DB0 Data Bit 0, LSB
17 CS Chip Select, active low.
18 R/W Enabled by CS, controls data read and write from the
input register.
PIN DESCRIPTIONS
PIN CONFIGURATION
PIN NAME DESCRIPTION
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
V
SS
V
OUT
Sense
V
OUT
RSTSEL
RST
LDAC
R/W
CS
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
DAC7641
V
DD
DGND
V
REFL
V
REFL
Sense
V
REFH
V
REFH
Sense
V
CC
AGND
32
31
30
29
28
27
26
25
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
9
10
11
12
13
14
15
16