Datasheet

16
®
DAC7641
DIGITAL INTERFACE
Table I shows the basic control logic for the DAC7641. Note
that the internal register is edge triggered and not level
triggered. When the LDAC signal is transitioned to HIGH,
the digital word currently in the register is latched.
The double-buffered architecture is designed so that the
DAC input register can be written to at any time.
FIGURE 12. Low Cost Single-Supply Configuration.
DIGITAL TIMING
Figure 14 and Table II provide detailed timing for the digital
interface of the DAC7641.
DIGITAL INPUT CODING
The DAC7641 input data is in Straight Binary format. The
output voltage is given by Equation 1.
INPUT
R/W CS RST RSTSEL LDAC REGISTER REGISTER MODE
L L H X X Write Hold Write Input
H L H X X Read Hold Read Input
XHH X Hold Write Update
X H H X H Hold Hold Hold
XX L X Reset to Zero Reset to Zero
XX H X Reset to Midscale Reset to Midscale
TABLE I. DAC7641 Logic Truth Table.
(1)
VVL
VHVLN
OUT REF
REF REF
=+
()
–•
,65 536
where N is the digital input code. This equation does not
include the effects of offset (zero-scale) or gain (full-scale)
errors.
+2.5V
+V
V
REFL
V
REFL
Sense
V
REFH
V
REFH
Sense
V
CC
AGND
30
29
28
27
26
25
DAC7641
V
OUT
Sense
V
OUT
V
SS
24
23
22
V
OUT
FIGURE 13. Linearity and Differential Linearity Error Curves
for Figure 12.
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(+25°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H