Datasheet

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DIGITAL INTERFACE
SERIAL DATA INPUT
DAC7634
SBAS134B – JULY 2004 – REVISED DECEMBER 2005
The DAC code, quick load control, and address are
provided via a 24-bit serial interface (see Figure 15 ).
Table 1 shows the basic control logic for the
The first two bits select the input register that is
DAC7634. The interface consists of a signal data
updated when LOAD goes LOW. The third bit is a
clock (CLK) input, serial data (SDI), DAC input
Quick Load bit such that if HIGH, the code in the shift
register load control signal ( LOAD), and DAC register
register is loaded into ALL DAC's input register when
load control signal (LDAC). In addition, a chip select
LOAD signal goes LOW. If the Quick Load bit is
( CS) input is available to enable serial communication
LOW, the content of shift register is loaded only to
when there are multiple serial devices. An
the DAC input register that is addressed. The Quick
asynchronous reset (RST) input, by the rising edge,
Load bit is followed by five unused bits. The last
is provided to simplify start-up conditions, periodic
sixteen bits (MSB first) are the DAC code.
resets, or emergency resets to a known state,
depending on the status of the reset select (RSTSEL)
signal.
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
QUICK
A1 A0 X X X X X D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LOAD
Table 1. DAC7634 Logic Truth Table
(1)
INPUT DAC
A1 A0 CS RST RSTSEL LDAC LOAD MODE DAC
REGISTER REGISTER
L L L H X X L Write Hold Write Input A
L H L H X X L Write Hold Write Input B
H L L H X X L Write Hold Write Input C
H H L H X X L Write Hold Write Input D
X X H H X ↑ H Hold Write Update All
X X H H X H H Hold Hold Hold All
X X X ↑ L X X Reset to Zero Reset to Zero Reset to Zero All
X X X ↑ H X X Reset to Midscale Reset to Midscale Reset to Midscale All
(1) If the DAC7634 is the only device on the serial bus, the CS pin can be connected to DGND permanently, which enables the shift register
all the time. In this case, only the CLK operates the serial shift register and all other functions listed in Table 1 should be followed as
shown. The DAC updates on the rising edge of LDAC.
The internal DAC register is edge-triggered and not gate, which controls the serial-to-parallel shift
level-triggered. When the LDAC signal is transitioned register. These two inputs are completely
from LOW to HIGH, the digital word currently in the interchangeable. In addition, care must be taken with
DAC input register is latched. The first set of registers the state of CLK when CS rises at the end of a serial
(the DAC input registers) are level-triggered via the transfer. If CLK is LOW when CS rises, the OR gate
LOAD signal. This double-buffered architecture has provides a rising edge to the shift register, shifting the
been designed so that new data can be entered for internal data one additional bit. The result will be
each DAC without disturbing the analog outputs. incorrect data and possible selection of the wrong
When the new data has been entered into the device, input register(s). If both CS and CLK are used, CS
all of the DAC outputs can be updated simultaneously should rise only when CLK is HIGH. If not, then either
by the rising edge of LDAC. Additionally, it allows the CS or CLK can be used to operate the shift register.
DAC input registers to be written to at any point, then See Table 2 for more information.
the DAC output voltages can be synchronously
changed via a trigger signal (LDAC).
Note that CS and CLK are combined with an OR
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