Datasheet

11
®
DAC7624/7625
DIGITAL TIMING
Figure 3 and Table II provide detailed timing for the digital
interface of the DAC7624 and DAC7625.
DIGITAL INPUT CODING
The DAC7624 and DAC7625 input data is in straight binary
format. The output voltage is given by the following equa-
tion:
where N is the digital input code. This equation does not
include the effects of offset (zero-scale) or gain (full-scale)
errors.
V
OUT
= V
REFL
+
V
REFH
–V
REFL
()
•N
4096
t
RCS
CS
t
RDS
t
RDH
t
AS
t
CSD
t
DZ
t
AH
R/W
A0/A1
Data Out
Data Valid
t
WCS
CS
t
WS
t
AS
t
AH
t
WH
R/W
A0/A1
t
RESET
t
LWD
t
LH
LDAC
t
DS
t
DH
t
LS
Data In
RESET
Data Output Timing
Digital Input Timing
FIGURE 3. Digital Input and Output Timing.
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
RCS
CS LOW for Read 200 ns
t
RDS
R/W HIGH to CS LOW 10 ns
t
RDH
R/W HIGH after CS HIGH 0 ns
t
DZ
CS HIGH to Data Bus in High Impedance 100 ns
t
CSD
CS LOW to Data Bus Valid 100 160 ns
t
WCS
CS LOW for Write 50 ns
t
WS
R/W LOW to CS LOW 0 ns
t
WH
R/W LOW after CS HIGH 0 ns
t
AS
Address Valid to CS LOW 0 ns
t
AH
Address Valid after CS HIGH 0 ns
t
LS
LDAC LOW to CS LOW 70 ns
t
LH
LDAC LOW after CS HIGH 50 ns
t
DS
Data Valid to CS LOW 0 ns
t
DH
Data Valid after CS HIGH 0 ns
t
LWD
LDAC LOW 50 ns
t
RESET
RESET LOW 50 ns
TABLE II. Timing Specifications (T
A
= –40°C to +85°C).