Datasheet

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DAC7574
SLAS375–JUNE 2003
Table 2. Control Byte
C7 C6 C5 C4 C3 C2 C1 C0 MSB7 MSB6 MSB5...
Don’t MSB MSB-1 MSB-2
0 0 Load1 Load0 Ch Sel 1 Ch Sel 0 PD0
Care (PD1) (PD2) ...LSB DESCRIPTION
(Address
Select)
Write to temporary
0 0 X 0 0 0 Data register A (TRA) with
data
Write to temporary
0 0 X 0 1 0 Data register B (TRB) with
data
Write to temporary
0 0 X 1 0 0 Data register C (TRC) with
data
Write to temporary
0 0 X 1 1 0 Data register D (TRD) with
data
(00, 01, 10, or 11) Write to TRx (selected
by C2 &C1
0 0 X 1 see Table 8 0
w/Powerdown Com-
mand
(00, 01, 10, or 11) Write to TRx (selected
0 1 X 0 Data by C2 &C1 and load
DACx w/data
(00, 01, 10, or 11) Power-down DACx
0 1 X 1 see Table 8 0 (selected by C2 and
C1)
(00, 01, 10, or 11) Write to TRx (selected
1 0 X 0 Data by C2 &C1 w/ data and
load all DACs
(00, 01, 10, or 11) Power-down DACx
1 0 X 1 see Table 8 0 (selected by C2 and
C1) & load all DACs
Broadcast Modes (controls up to 4 devices on a single serial bus)
Update all DACs, all
X X 1 1 X 0 X X X devices with previously
stored TRx data
Update all DACs, all
X X 1 1 X 1 X 0 Data devices with MSB[7:0]
and LSB[7:0] data
Power-down all DACs,
X X 1 1 X 1 X 1 see Table 8 0
all devices
Most Significant Byte
Most Significant Byte MSB[7:0] consists of eight most significant bits of 12-bit unsigned binary D/A conversion
data. C0=1, MSB[7], MSB[6] indicate a powerdown operation as shown in Table 8.
Least Significant Byte
Least Significant Byte LSB[7:0] consists of the 4 least significant bits of the 12-bit unsigned binary D/A
conversion data, followed by 4 don’t care bits. DAC7574 updates at the falling edge of the acknowledge signal
that follows the LSB[0] bit.
Default Readback Condition
If the user initiates a readback of a specified channel without first writing data to that specified channel, the
default readback is all zeros, since the readback register is initialized to 0 during the power on reset phase.
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