Datasheet

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Master Receiver Reading From a Slave Transmitter (DAC7573) in Standard/Fast Modes
DAC7573
SLAS398 – SEPTEMBER 2003
When reading data back from the DAC7573, the user begins with an address byte (with R/ W = 0) after which the
DAC7573 will acknowledge by pulling SDA low. This address byte is usually followed by the Control Byte, which
is also acknowledged by the DAC7573. Following this there is a REPEATED START condition by the Master and
the address is resent with (R/ W = 1). This is acknowledged by the DAC7573, indicating that it is prepared to
transmit data. Two or three bytes of data are then read back from the DAC7573, depending on the (PD0-Bit).
The value of Buff-Sel1 and Buff-Sel0 determines, which channel data is read back. A STOP Condition follows.
With the (PD0-Bit = 0) the DAC7573 transmits 2 bytes of data, HIGH-BYTE followed by the LOW-BYTE (refer to
Table 2. Data Readback Mode - 2 bytes).
With the (PD0-Bit = 1) the DAC7573 transmits 3 bytes of data, POWER-DOWN-BYTE followed by the
HIGH-BYTE followed by the LOW-BYTE (refer to Table 2. Data Readback Mode - 3 bytes).
Table 6. Read Sequence in F/S Mode
DATA READBACK MODE - 2 BYTES
Transmitter MSB 6 5 4 3 2 1 LSB Comment
Master Start Begin sequence
Master 1 0 0 1 1 A1 A0 R/ W Write addressing ( R/ W=0)
DAC7573 DAC7573 acknowledges
Master A3 A2 Load 1 Load 0 x Buff Sel 1 Buff Sel 0 PD0 Control byte ( PD0=0)
DAC7573 DAC7573 acknowledges
Master Repeated start
Master 1 0 0 1 1 A1 A0 R/ W Read addressing ( R/ W = 1)
DAC7573 DAC7573 acknowledges
DAC7573 D11 D10 D9 D8 D7 D6 D5 D4 Reading data word, high byte
Master Master acknowledges
DAC7573 D3 D2 D1 D0 x x x x Reading data word, low byte
Master Master not acknowledges Master signal end of read
Master Stop or repeated start
(1)
Done
DATA READBACK MODE - 3 BYTES
Transmitter MSB 6 5 4 3 2 1 LSB Comment
Master Start Begin sequence
Master 1 0 0 1 1 A1 A0 R/ W Write addressing ( R/ W=0)
DAC7573 DAC7573 acknowledges
Master A3 A2 Load 1 Load 0 x Buff Sel 1 Buff Sel 0 PD0 Control byte ( PD0=1)
DAC7573 DAC7573 acknowledges
Master Repeated start
Master 1 0 0 1 1 A1 A0 R/ W Read addressing ( R/ W = 1)
DAC7573 DAC7573 acknowledges
DAC7573 PD1 PD2 1 1 1 1 1 1 Read power down byte
Master Master acknowledges
DAC7573 D11 D10 D9 D8 D7 D6 D5 D4 Reading data word, high byte
Master Master acknowledges
DAC7573 D3 D2 D1 D0 x x x x Reading data word, low byte
Master Master not acknowledges Master signal end of read
Master Stop or repeated start
(1)
Done
(1) Use repeated start to secure bus operation and loop back to the stage of write addressing for next Write.
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