Datasheet

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Change of Data Allowed
Data Line
Stable;
Data Valid
SDA
SCL
Recognize START or
REPEATED START
Condition
Recognize STOP or
REPEATED START
Condition
Generate ACKNOWLEDGE
Signal
Acknowledgement
Signal From Slave
SDA
SCL
MSB
P
Sr
Sr
or
P
S
or
Sr
START or
Repeated START
Condition
STOP or
Repeated START
Condition
Clock Line Held Low While
Interrupts are Serviced
1 2 7 8 9
ACK
1 2 3 - 8 9
ACK
Address
R/W
DAC7571
SLAS374C – FEBRUARY 2003 – REVISED MAY 2006
THEORY OF OPERATION (continued)
Figure 43. Bit Transfer on the I
2
C Bus
• When all data bits have been written, a Stop condition is established (see Figure 44 ). In writing to the
DAC7571, the master must pull the SDA line high during the tenth clock pulse to establish a Stop condition.
Figure 44. Bus Protocol
14
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