Datasheet

www.ti.com
OUTPUT AMPLIFIER
I
2
C Interface
Start
Condition
SDA
Stop
Condition
SDA
SCL
S P
SCL
Not Acknowledge
Acknowledge
1 2 8 9
Clock Pulse for
Acknowledgement
S
START
Condition
Data Output
by Transmitter
Data Output
by Receiver
SCL From
Master
DAC7571
SLAS374C – FEBRUARY 2003 – REVISED MAY 2006
THEORY OF OPERATION (continued)
The output buffer amplifier is capable of generating rail-to-rail voltages on its output which gives an output range
of 0 V to V
DD
. It is capable of driving a load of 2k Ω in parallel with 1000 pF to GND. The source and sink
capabilities of the output amplifier can be seen in the typical characteristics. The slew rate is 1V/µs with a
half-scale settling time of 8 µs with the output unloaded.
The DAC7571 uses an I
2
C interface as defined by Philips Semiconductor to receive data in slave mode (see
I
2
C-Bus Specification, Version 2.1, January 2000). The DAC7571 supports the following data transfer modes,
described in the I
2
C-Bus Specification: Standard Mode (100 kbit/s), Fast Mode (400 kbit/s) and High-Speed
Mode (3.4 Mbit/s). Ten-bit addressing and general call addres are not supported.
For simplicity, standard mode and fast mode are referred to as F/S-mode and high-speed mode is referred tg as
HS-mode.
The 2-wire I
2
C serial bus protocol operates as follows:
• The Master initiates data transfer by establishing a Start condition. The Start condition is defined when a
high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure 41 . The byte following
the start condition is the address byte consisting of the 7-bit slave address followed by the W bit.
Figure 41. START and STOP Conditions
• The addressed Slave responds by pulling the SDA pin low during the ninth clock pulse, termed the
Acknowledge bit (see Figure 42 ). At this stage all other devices on the bus remain idle while the selected
device waits for data to be written to its shift register.
Figure 42. Acknowledge on the I
2
C Bus
• Data is transmitted over the serial bus in sequences of nine clock cycles (8 data bits followed by an
acknowledge bit. The transitions on the SDA line must occur during the low period of SCL and remain stable
during the high period of SCL (see Figure 43 ).
13
Submit Documentation Feedback