Datasheet

EVM Overview

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1 EVM Overview

• Full-featured Evaluation Board for the 12-/14-/16-bit, eight-channel DAC7568, DAC8168, or DAC8568

digital-to-analog converters

• Onboard reference and buffer circuits

• High-speed serial interface

• Modular design for use with a variety of DSP and DACxx68 DAC Controller Interface Boards

2 Analog Interface

For maximum flexibility, the DACxx68EVM is designed for easy interfacing to multiple analog sources.

Samtec part numbers SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a convenient 10-pin,

dual-row header/socket combination at J2. This header/socket provides access to the analog input pins of

the ADC. Consult Samtec at www.samtec.com or call 1-800-SAMTEC-9 for a variety of mating connector

options.

Pin Number Signal Description

J2.2 DAC OUT_G Voltage output for DAC channel G

J2.4 DAC OUT_E Voltage output for DAC channel E

J2.6 DAC OUT_C Voltage output for DAC channel C

J2.8 DAC OUT_A Voltage output for DAC channel A

J2.10 DAC OUT_B Voltage output for DAC channel B

J2.12 DAC OUT_D Voltage output for DAC channel D

J2.14 DAC OUT_F Voltage output for DAC channel F

J2.16 DAC OUT_H Voltage output for DAC channel H

J2.18 REF(–) Unused

J2.20 REF(+) External reference source input (2.5 V NOM, 2.525 V maximum)

J2.15 VCOM Common-mode voltage output option

J2.1–J2.19 (odd) AGND Analog ground connections (except J2.15)

3 Digital Interface

The DACxx68EVM is designed for easy interfacing to multiple control platforms. Samtec part numbers

SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a convenient 10-pin, dual-row header/socket

combination at J2. This header/socket provides access to the digital control and serial data pins of the

DACxx68 DAC EVM. Consult Samtec at www.samtec.com or 1-800-SAMTEC-9 for a variety of mating

connector options.

Table 1. Digital Control

Pin Number Signal Description

J2.1 CNTL Active-low input to SYNC enables data transfer – jumper configurable (see schematic) via JP5

J2.3 SCLK Serial clock

J2.5 SCLK(R) Serial clock return (for DSP host systems)

J2.7 FSX Frame synchronization for DSP host systems – default SYNC input through JP5 (see schematic)

J2.9 FS(R) Frame synchronization return (for DSP host systems)

J2.11 DX Serial data input

J2.13 DR Unused – Serial data return (for DSP host systems)

J2.15 INT External source for LOAD DAC (LDAC) strobe via JP6

J2.17 TOUT Default source for LOAD DAC (LDAC) strobe via JP6

J2.19 GPIO5 Optional source for active low CLEAR (CLR) input

DACxx68EVM SLAU301–November 2009

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