Datasheet

CLK
SYNC
D
IN
ValidWriteSequence:
Output/ModeUpdates onthe24thFallingEdge
24thFallingEdge 24thFallingEdge
DB23 DB0 DB23 DB0
Invalid/InterruptedWriteSequence:
Output/ModeDoesNotUpdate onthe24thFallingEdge
DAC7565
www.ti.com SBAS412B –FEBRUARY 2008–REVISED MARCH 2011
SYNC INTERRUPT LDAC FUNCTIONALITY
In a normal write sequence, the SYNC line stays low The DAC7565 offers both a software and hardware
for at least 24 falling edges of SCLK and the simultaneous update function. The DAC
addressed DAC register updates on the 24th falling double-buffered architecture has been designed so
edge. However, if SYNC is brought high before the that new data can be entered for each DAC without
24th falling edge, it acts as an interrupt to the write disturbing the analog outputs.
sequence; the shift register resets and the write
DAC7565 data updates are synchronized with the
sequence is discarded. Neither an update of the data
falling edge of the 24th SCLK cycle, which follows a
buffer contents, DAC register contents, nor a change
falling edge of SYNC. For such synchronous updates,
in the operating mode occurs (as shown in
the LDAC pin is not required and it must be
Figure 95).
connected to GND permanently. The LDAC pin is
used as a positive edge triggered timing signal for
POWER-ON RESET TO ZERO-SCALE OR
asynchronous DAC updates. To do an LDAC
MID-SCALE
operation, single-channel store(s) should be done
(loading DAC buffers) by setting LD0 and LD1 to '0'.
The DAC7565 contains a power-on reset circuit that
Multiple single-channel updates can be done in order
controls the output voltage during power-up.
to set different channel buffers to desired values and
Depending on the RSTSEL signal, on power-up, the
then make a rising edge on LDAC. Data buffers of all
DAC registers are reset and the output voltages are
channels must be loaded with desired data before an
set to zero-scale (RSTSEL = 0) or mid-scale
LDAC rising edge. After a low-to-high LDAC
(RSTSEL = 1); they remain that way until a valid write
transition, all DACs are simultaneously updated with
sequence and load command are made to the
the contents of the corresponding data buffers. If the
respective DAC channel. The power-on reset is
contents of a data buffer are not changed by the
useful in applications where it is important to know
serial interface, the corresponding DAC output
the state of the output of each DAC while the device
remains unchanged after the LDAC trigger.
is in the process of powering up.
No device pin should be brought high before power is
ENABLE PIN
applied to the device. The internal reference is
powered on by default and remains that way until a For normal operation, the enable pin must be driven
valid reference-change command is executed. to a logic low. If the enable pin is driven high, the
DAC7565 stops listening to the serial port. However,
SCLK, SYNC, and D
IN
must not be kept floating, but
must be at some logic level. This feature can be
useful for applications that share the same serial port.
Figure 95. SYNC Interrupt Facility
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